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@@ -14,451 +14,285 @@
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* GNU General Public License for more details.
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*/
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-#include <sound/soc.h>
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-#include <linux/regmap.h>
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-#include <linux/pm_runtime.h>
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-
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#include "mt2701-afe-common.h"
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#include "mt2701-afe-clock-ctrl.h"
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-static const char *aud_clks[MT2701_CLOCK_NUM] = {
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- [MT2701_AUD_INFRA_SYS_AUDIO] = "infra_sys_audio_clk",
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- [MT2701_AUD_AUD_MUX1_SEL] = "top_audio_mux1_sel",
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- [MT2701_AUD_AUD_MUX2_SEL] = "top_audio_mux2_sel",
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- [MT2701_AUD_AUD_MUX1_DIV] = "top_audio_mux1_div",
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- [MT2701_AUD_AUD_MUX2_DIV] = "top_audio_mux2_div",
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- [MT2701_AUD_AUD_48K_TIMING] = "top_audio_48k_timing",
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- [MT2701_AUD_AUD_44K_TIMING] = "top_audio_44k_timing",
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- [MT2701_AUD_AUDPLL_MUX_SEL] = "top_audpll_mux_sel",
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- [MT2701_AUD_APLL_SEL] = "top_apll_sel",
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- [MT2701_AUD_AUD1PLL_98M] = "top_aud1_pll_98M",
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- [MT2701_AUD_AUD2PLL_90M] = "top_aud2_pll_90M",
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- [MT2701_AUD_HADDS2PLL_98M] = "top_hadds2_pll_98M",
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- [MT2701_AUD_HADDS2PLL_294M] = "top_hadds2_pll_294M",
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- [MT2701_AUD_AUDPLL] = "top_audpll",
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- [MT2701_AUD_AUDPLL_D4] = "top_audpll_d4",
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- [MT2701_AUD_AUDPLL_D8] = "top_audpll_d8",
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- [MT2701_AUD_AUDPLL_D16] = "top_audpll_d16",
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- [MT2701_AUD_AUDPLL_D24] = "top_audpll_d24",
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- [MT2701_AUD_AUDINTBUS] = "top_audintbus_sel",
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- [MT2701_AUD_CLK_26M] = "clk_26m",
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- [MT2701_AUD_SYSPLL1_D4] = "top_syspll1_d4",
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- [MT2701_AUD_AUD_K1_SRC_SEL] = "top_aud_k1_src_sel",
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- [MT2701_AUD_AUD_K2_SRC_SEL] = "top_aud_k2_src_sel",
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- [MT2701_AUD_AUD_K3_SRC_SEL] = "top_aud_k3_src_sel",
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- [MT2701_AUD_AUD_K4_SRC_SEL] = "top_aud_k4_src_sel",
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- [MT2701_AUD_AUD_K5_SRC_SEL] = "top_aud_k5_src_sel",
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- [MT2701_AUD_AUD_K6_SRC_SEL] = "top_aud_k6_src_sel",
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- [MT2701_AUD_AUD_K1_SRC_DIV] = "top_aud_k1_src_div",
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- [MT2701_AUD_AUD_K2_SRC_DIV] = "top_aud_k2_src_div",
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- [MT2701_AUD_AUD_K3_SRC_DIV] = "top_aud_k3_src_div",
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- [MT2701_AUD_AUD_K4_SRC_DIV] = "top_aud_k4_src_div",
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- [MT2701_AUD_AUD_K5_SRC_DIV] = "top_aud_k5_src_div",
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- [MT2701_AUD_AUD_K6_SRC_DIV] = "top_aud_k6_src_div",
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- [MT2701_AUD_AUD_I2S1_MCLK] = "top_aud_i2s1_mclk",
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- [MT2701_AUD_AUD_I2S2_MCLK] = "top_aud_i2s2_mclk",
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- [MT2701_AUD_AUD_I2S3_MCLK] = "top_aud_i2s3_mclk",
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- [MT2701_AUD_AUD_I2S4_MCLK] = "top_aud_i2s4_mclk",
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- [MT2701_AUD_AUD_I2S5_MCLK] = "top_aud_i2s5_mclk",
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- [MT2701_AUD_AUD_I2S6_MCLK] = "top_aud_i2s6_mclk",
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- [MT2701_AUD_ASM_M_SEL] = "top_asm_m_sel",
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- [MT2701_AUD_ASM_H_SEL] = "top_asm_h_sel",
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- [MT2701_AUD_UNIVPLL2_D4] = "top_univpll2_d4",
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- [MT2701_AUD_UNIVPLL2_D2] = "top_univpll2_d2",
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- [MT2701_AUD_SYSPLL_D5] = "top_syspll_d5",
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+static const char *const base_clks[] = {
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+ [MT2701_INFRA_SYS_AUDIO] = "infra_sys_audio_clk",
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+ [MT2701_TOP_AUD_MCLK_SRC0] = "top_audio_mux1_sel",
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+ [MT2701_TOP_AUD_MCLK_SRC1] = "top_audio_mux2_sel",
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+ [MT2701_TOP_AUD_A1SYS] = "top_audio_a1sys_hp",
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+ [MT2701_TOP_AUD_A2SYS] = "top_audio_a2sys_hp",
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+ [MT2701_AUDSYS_AFE] = "audio_afe_pd",
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+ [MT2701_AUDSYS_AFE_CONN] = "audio_afe_conn_pd",
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+ [MT2701_AUDSYS_A1SYS] = "audio_a1sys_pd",
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+ [MT2701_AUDSYS_A2SYS] = "audio_a2sys_pd",
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};
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int mt2701_init_clock(struct mtk_base_afe *afe)
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{
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struct mt2701_afe_private *afe_priv = afe->platform_priv;
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- int i = 0;
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-
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- for (i = 0; i < MT2701_CLOCK_NUM; i++) {
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- afe_priv->clocks[i] = devm_clk_get(afe->dev, aud_clks[i]);
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- if (IS_ERR(afe_priv->clocks[i])) {
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- dev_warn(afe->dev, "%s devm_clk_get %s fail\n",
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- __func__, aud_clks[i]);
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- return PTR_ERR(aud_clks[i]);
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+ int i;
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+
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+ for (i = 0; i < MT2701_BASE_CLK_NUM; i++) {
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+ afe_priv->base_ck[i] = devm_clk_get(afe->dev, base_clks[i]);
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+ if (IS_ERR(afe_priv->base_ck[i])) {
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+ dev_err(afe->dev, "failed to get %s\n", base_clks[i]);
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+ return PTR_ERR(afe_priv->base_ck[i]);
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+ }
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+ }
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+
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+ /* Get I2S related clocks */
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+ for (i = 0; i < MT2701_I2S_NUM; i++) {
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+ struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[i];
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+ char name[13];
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+
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+ snprintf(name, sizeof(name), "i2s%d_src_sel", i);
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+ i2s_path->sel_ck = devm_clk_get(afe->dev, name);
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+ if (IS_ERR(i2s_path->sel_ck)) {
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+ dev_err(afe->dev, "failed to get %s\n", name);
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+ return PTR_ERR(i2s_path->sel_ck);
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+ }
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+
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+ snprintf(name, sizeof(name), "i2s%d_src_div", i);
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+ i2s_path->div_ck = devm_clk_get(afe->dev, name);
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+ if (IS_ERR(i2s_path->div_ck)) {
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+ dev_err(afe->dev, "failed to get %s\n", name);
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+ return PTR_ERR(i2s_path->div_ck);
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+ }
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+
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+ snprintf(name, sizeof(name), "i2s%d_mclk_en", i);
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+ i2s_path->mclk_ck = devm_clk_get(afe->dev, name);
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+ if (IS_ERR(i2s_path->mclk_ck)) {
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+ dev_err(afe->dev, "failed to get %s\n", name);
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+ return PTR_ERR(i2s_path->mclk_ck);
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+ }
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+
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+ snprintf(name, sizeof(name), "i2so%d_hop_ck", i);
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+ i2s_path->hop_ck[I2S_OUT] = devm_clk_get(afe->dev, name);
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+ if (IS_ERR(i2s_path->hop_ck[I2S_OUT])) {
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+ dev_err(afe->dev, "failed to get %s\n", name);
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+ return PTR_ERR(i2s_path->hop_ck[I2S_OUT]);
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+ }
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+
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+ snprintf(name, sizeof(name), "i2si%d_hop_ck", i);
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+ i2s_path->hop_ck[I2S_IN] = devm_clk_get(afe->dev, name);
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+ if (IS_ERR(i2s_path->hop_ck[I2S_IN])) {
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+ dev_err(afe->dev, "failed to get %s\n", name);
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+ return PTR_ERR(i2s_path->hop_ck[I2S_IN]);
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+ }
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+
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+ snprintf(name, sizeof(name), "asrc%d_out_ck", i);
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+ i2s_path->asrco_ck = devm_clk_get(afe->dev, name);
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+ if (IS_ERR(i2s_path->asrco_ck)) {
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+ dev_err(afe->dev, "failed to get %s\n", name);
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+ return PTR_ERR(i2s_path->asrco_ck);
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}
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}
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+ /* Some platforms may support BT path */
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+ afe_priv->mrgif_ck = devm_clk_get(afe->dev, "audio_mrgif_pd");
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+ if (IS_ERR(afe_priv->mrgif_ck)) {
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+ if (PTR_ERR(afe_priv->mrgif_ck) == -EPROBE_DEFER)
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+ return -EPROBE_DEFER;
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+
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+ afe_priv->mrgif_ck = NULL;
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+ }
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+
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return 0;
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}
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-int mt2701_afe_enable_clock(struct mtk_base_afe *afe)
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+int mt2701_afe_enable_i2s(struct mtk_base_afe *afe, int id, int dir)
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{
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- int ret = 0;
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+ struct mt2701_afe_private *afe_priv = afe->platform_priv;
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+ struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id];
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+ int ret;
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- ret = mt2701_turn_on_a1sys_clock(afe);
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+ ret = clk_prepare_enable(i2s_path->asrco_ck);
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if (ret) {
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- dev_err(afe->dev, "%s turn_on_a1sys_clock fail %d\n",
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- __func__, ret);
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+ dev_err(afe->dev, "failed to enable ASRC clock %d\n", ret);
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return ret;
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}
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- ret = mt2701_turn_on_a2sys_clock(afe);
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+ ret = clk_prepare_enable(i2s_path->hop_ck[dir]);
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if (ret) {
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- dev_err(afe->dev, "%s turn_on_a2sys_clock fail %d\n",
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- __func__, ret);
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- mt2701_turn_off_a1sys_clock(afe);
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- return ret;
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+ dev_err(afe->dev, "failed to enable I2S clock %d\n", ret);
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+ goto err_hop_ck;
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}
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- ret = mt2701_turn_on_afe_clock(afe);
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- if (ret) {
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- dev_err(afe->dev, "%s turn_on_afe_clock fail %d\n",
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- __func__, ret);
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- mt2701_turn_off_a1sys_clock(afe);
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- mt2701_turn_off_a2sys_clock(afe);
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- return ret;
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- }
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+ return 0;
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- regmap_update_bits(afe->regmap, ASYS_TOP_CON,
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- AUDIO_TOP_CON0_A1SYS_A2SYS_ON,
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- AUDIO_TOP_CON0_A1SYS_A2SYS_ON);
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- regmap_update_bits(afe->regmap, AFE_DAC_CON0,
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- AFE_DAC_CON0_AFE_ON,
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- AFE_DAC_CON0_AFE_ON);
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- regmap_write(afe->regmap, PWR2_TOP_CON,
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- PWR2_TOP_CON_INIT_VAL);
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- regmap_write(afe->regmap, PWR1_ASM_CON1,
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- PWR1_ASM_CON1_INIT_VAL);
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- regmap_write(afe->regmap, PWR2_ASM_CON1,
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- PWR2_ASM_CON1_INIT_VAL);
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+err_hop_ck:
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+ clk_disable_unprepare(i2s_path->asrco_ck);
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- return 0;
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+ return ret;
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}
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-void mt2701_afe_disable_clock(struct mtk_base_afe *afe)
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+void mt2701_afe_disable_i2s(struct mtk_base_afe *afe, int id, int dir)
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{
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- mt2701_turn_off_afe_clock(afe);
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- mt2701_turn_off_a1sys_clock(afe);
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- mt2701_turn_off_a2sys_clock(afe);
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- regmap_update_bits(afe->regmap, ASYS_TOP_CON,
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- AUDIO_TOP_CON0_A1SYS_A2SYS_ON, 0);
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- regmap_update_bits(afe->regmap, AFE_DAC_CON0,
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- AFE_DAC_CON0_AFE_ON, 0);
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+ struct mt2701_afe_private *afe_priv = afe->platform_priv;
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+ struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id];
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+
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+ clk_disable_unprepare(i2s_path->hop_ck[dir]);
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+ clk_disable_unprepare(i2s_path->asrco_ck);
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}
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-int mt2701_turn_on_a1sys_clock(struct mtk_base_afe *afe)
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+int mt2701_afe_enable_mclk(struct mtk_base_afe *afe, int id)
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{
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struct mt2701_afe_private *afe_priv = afe->platform_priv;
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- int ret = 0;
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-
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- /* Set Mux */
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- ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL]);
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- if (ret) {
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- dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
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- __func__, aud_clks[MT2701_AUD_AUD_MUX1_SEL], ret);
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- goto A1SYS_CLK_AUD_MUX1_SEL_ERR;
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- }
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-
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- ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL],
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- afe_priv->clocks[MT2701_AUD_AUD1PLL_98M]);
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- if (ret) {
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- dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__,
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- aud_clks[MT2701_AUD_AUD_MUX1_SEL],
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- aud_clks[MT2701_AUD_AUD1PLL_98M], ret);
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- goto A1SYS_CLK_AUD_MUX1_SEL_ERR;
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- }
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-
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- /* Set Divider */
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- ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_MUX1_DIV]);
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- if (ret) {
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- dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
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- __func__,
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- aud_clks[MT2701_AUD_AUD_MUX1_DIV],
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- ret);
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- goto A1SYS_CLK_AUD_MUX1_DIV_ERR;
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- }
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-
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- ret = clk_set_rate(afe_priv->clocks[MT2701_AUD_AUD_MUX1_DIV],
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- MT2701_AUD_AUD_MUX1_DIV_RATE);
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- if (ret) {
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- dev_err(afe->dev, "%s clk_set_parent %s-%d fail %d\n", __func__,
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- aud_clks[MT2701_AUD_AUD_MUX1_DIV],
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- MT2701_AUD_AUD_MUX1_DIV_RATE, ret);
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- goto A1SYS_CLK_AUD_MUX1_DIV_ERR;
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- }
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+ struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id];
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- /* Enable clock gate */
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- ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_48K_TIMING]);
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- if (ret) {
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- dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
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- __func__, aud_clks[MT2701_AUD_AUD_48K_TIMING], ret);
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- goto A1SYS_CLK_AUD_48K_ERR;
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- }
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+ return clk_prepare_enable(i2s_path->mclk_ck);
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+}
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- /* Enable infra audio */
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- ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
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- if (ret) {
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- dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
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- __func__, aud_clks[MT2701_AUD_INFRA_SYS_AUDIO], ret);
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- goto A1SYS_CLK_INFRA_ERR;
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- }
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+void mt2701_afe_disable_mclk(struct mtk_base_afe *afe, int id)
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+{
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+ struct mt2701_afe_private *afe_priv = afe->platform_priv;
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+ struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id];
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- return 0;
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+ clk_disable_unprepare(i2s_path->mclk_ck);
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+}
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-A1SYS_CLK_INFRA_ERR:
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- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
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-A1SYS_CLK_AUD_48K_ERR:
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- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_48K_TIMING]);
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-A1SYS_CLK_AUD_MUX1_DIV_ERR:
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- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX1_DIV]);
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-A1SYS_CLK_AUD_MUX1_SEL_ERR:
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- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL]);
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+int mt2701_enable_btmrg_clk(struct mtk_base_afe *afe)
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+{
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+ struct mt2701_afe_private *afe_priv = afe->platform_priv;
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- return ret;
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|
+ return clk_prepare_enable(afe_priv->mrgif_ck);
|
|
|
}
|
|
|
|
|
|
-void mt2701_turn_off_a1sys_clock(struct mtk_base_afe *afe)
|
|
|
+void mt2701_disable_btmrg_clk(struct mtk_base_afe *afe)
|
|
|
{
|
|
|
struct mt2701_afe_private *afe_priv = afe->platform_priv;
|
|
|
|
|
|
- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
|
|
|
- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_48K_TIMING]);
|
|
|
- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX1_DIV]);
|
|
|
- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL]);
|
|
|
+ clk_disable_unprepare(afe_priv->mrgif_ck);
|
|
|
}
|
|
|
|
|
|
-int mt2701_turn_on_a2sys_clock(struct mtk_base_afe *afe)
|
|
|
+static int mt2701_afe_enable_audsys(struct mtk_base_afe *afe)
|
|
|
{
|
|
|
struct mt2701_afe_private *afe_priv = afe->platform_priv;
|
|
|
- int ret = 0;
|
|
|
+ int ret;
|
|
|
|
|
|
- /* Set Mux */
|
|
|
- ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL]);
|
|
|
- if (ret) {
|
|
|
- dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
|
|
|
- __func__, aud_clks[MT2701_AUD_AUD_MUX2_SEL], ret);
|
|
|
- goto A2SYS_CLK_AUD_MUX2_SEL_ERR;
|
|
|
- }
|
|
|
+ /* Enable infra clock gate */
|
|
|
+ ret = clk_prepare_enable(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
|
|
|
- ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL],
|
|
|
- afe_priv->clocks[MT2701_AUD_AUD2PLL_90M]);
|
|
|
- if (ret) {
|
|
|
- dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__,
|
|
|
- aud_clks[MT2701_AUD_AUD_MUX2_SEL],
|
|
|
- aud_clks[MT2701_AUD_AUD2PLL_90M], ret);
|
|
|
- goto A2SYS_CLK_AUD_MUX2_SEL_ERR;
|
|
|
- }
|
|
|
+ /* Enable top a1sys clock gate */
|
|
|
+ ret = clk_prepare_enable(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
|
|
|
+ if (ret)
|
|
|
+ goto err_a1sys;
|
|
|
|
|
|
- /* Set Divider */
|
|
|
- ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_MUX2_DIV]);
|
|
|
- if (ret) {
|
|
|
- dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
|
|
|
- __func__, aud_clks[MT2701_AUD_AUD_MUX2_DIV], ret);
|
|
|
- goto A2SYS_CLK_AUD_MUX2_DIV_ERR;
|
|
|
- }
|
|
|
+ /* Enable top a2sys clock gate */
|
|
|
+ ret = clk_prepare_enable(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
|
|
|
+ if (ret)
|
|
|
+ goto err_a2sys;
|
|
|
|
|
|
- ret = clk_set_rate(afe_priv->clocks[MT2701_AUD_AUD_MUX2_DIV],
|
|
|
- MT2701_AUD_AUD_MUX2_DIV_RATE);
|
|
|
- if (ret) {
|
|
|
- dev_err(afe->dev, "%s clk_set_parent %s-%d fail %d\n", __func__,
|
|
|
- aud_clks[MT2701_AUD_AUD_MUX2_DIV],
|
|
|
- MT2701_AUD_AUD_MUX2_DIV_RATE, ret);
|
|
|
- goto A2SYS_CLK_AUD_MUX2_DIV_ERR;
|
|
|
- }
|
|
|
+ /* Internal clock gates */
|
|
|
+ ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
|
|
|
+ if (ret)
|
|
|
+ goto err_afe;
|
|
|
|
|
|
- /* Enable clock gate */
|
|
|
- ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_44K_TIMING]);
|
|
|
- if (ret) {
|
|
|
- dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
|
|
|
- __func__, aud_clks[MT2701_AUD_AUD_44K_TIMING], ret);
|
|
|
- goto A2SYS_CLK_AUD_44K_ERR;
|
|
|
- }
|
|
|
+ ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
|
|
|
+ if (ret)
|
|
|
+ goto err_audio_a1sys;
|
|
|
|
|
|
- /* Enable infra audio */
|
|
|
- ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
|
|
|
- if (ret) {
|
|
|
- dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
|
|
|
- __func__, aud_clks[MT2701_AUD_INFRA_SYS_AUDIO], ret);
|
|
|
- goto A2SYS_CLK_INFRA_ERR;
|
|
|
- }
|
|
|
+ ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]);
|
|
|
+ if (ret)
|
|
|
+ goto err_audio_a2sys;
|
|
|
+
|
|
|
+ ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE_CONN]);
|
|
|
+ if (ret)
|
|
|
+ goto err_afe_conn;
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
-A2SYS_CLK_INFRA_ERR:
|
|
|
- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
|
|
|
-A2SYS_CLK_AUD_44K_ERR:
|
|
|
- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_44K_TIMING]);
|
|
|
-A2SYS_CLK_AUD_MUX2_DIV_ERR:
|
|
|
- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX2_DIV]);
|
|
|
-A2SYS_CLK_AUD_MUX2_SEL_ERR:
|
|
|
- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL]);
|
|
|
+err_afe_conn:
|
|
|
+ clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]);
|
|
|
+err_audio_a2sys:
|
|
|
+ clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
|
|
|
+err_audio_a1sys:
|
|
|
+ clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
|
|
|
+err_afe:
|
|
|
+ clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
|
|
|
+err_a2sys:
|
|
|
+ clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
|
|
|
+err_a1sys:
|
|
|
+ clk_disable_unprepare(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
|
|
|
|
|
|
return ret;
|
|
|
}
|
|
|
|
|
|
-void mt2701_turn_off_a2sys_clock(struct mtk_base_afe *afe)
|
|
|
+static void mt2701_afe_disable_audsys(struct mtk_base_afe *afe)
|
|
|
{
|
|
|
struct mt2701_afe_private *afe_priv = afe->platform_priv;
|
|
|
|
|
|
- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
|
|
|
- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_44K_TIMING]);
|
|
|
- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX2_DIV]);
|
|
|
- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL]);
|
|
|
+ clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE_CONN]);
|
|
|
+ clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]);
|
|
|
+ clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
|
|
|
+ clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
|
|
|
+ clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
|
|
|
+ clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
|
|
|
+ clk_disable_unprepare(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
|
|
|
}
|
|
|
|
|
|
-int mt2701_turn_on_afe_clock(struct mtk_base_afe *afe)
|
|
|
+int mt2701_afe_enable_clock(struct mtk_base_afe *afe)
|
|
|
{
|
|
|
- struct mt2701_afe_private *afe_priv = afe->platform_priv;
|
|
|
int ret;
|
|
|
|
|
|
- /* enable INFRA_SYS */
|
|
|
- ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
|
|
|
- if (ret) {
|
|
|
- dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
|
|
|
- __func__, aud_clks[MT2701_AUD_INFRA_SYS_AUDIO], ret);
|
|
|
- goto AFE_AUD_INFRA_ERR;
|
|
|
- }
|
|
|
-
|
|
|
- /* Set MT2701_AUD_AUDINTBUS to MT2701_AUD_SYSPLL1_D4 */
|
|
|
- ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUDINTBUS]);
|
|
|
- if (ret) {
|
|
|
- dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
|
|
|
- __func__, aud_clks[MT2701_AUD_AUDINTBUS], ret);
|
|
|
- goto AFE_AUD_AUDINTBUS_ERR;
|
|
|
- }
|
|
|
-
|
|
|
- ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_AUDINTBUS],
|
|
|
- afe_priv->clocks[MT2701_AUD_SYSPLL1_D4]);
|
|
|
- if (ret) {
|
|
|
- dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__,
|
|
|
- aud_clks[MT2701_AUD_AUDINTBUS],
|
|
|
- aud_clks[MT2701_AUD_SYSPLL1_D4], ret);
|
|
|
- goto AFE_AUD_AUDINTBUS_ERR;
|
|
|
- }
|
|
|
-
|
|
|
- /* Set MT2701_AUD_ASM_H_SEL to MT2701_AUD_UNIVPLL2_D2 */
|
|
|
- ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_ASM_H_SEL]);
|
|
|
+ /* Enable audio system */
|
|
|
+ ret = mt2701_afe_enable_audsys(afe);
|
|
|
if (ret) {
|
|
|
- dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
|
|
|
- __func__, aud_clks[MT2701_AUD_ASM_H_SEL], ret);
|
|
|
- goto AFE_AUD_ASM_H_ERR;
|
|
|
- }
|
|
|
-
|
|
|
- ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_ASM_H_SEL],
|
|
|
- afe_priv->clocks[MT2701_AUD_UNIVPLL2_D2]);
|
|
|
- if (ret) {
|
|
|
- dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__,
|
|
|
- aud_clks[MT2701_AUD_ASM_H_SEL],
|
|
|
- aud_clks[MT2701_AUD_UNIVPLL2_D2], ret);
|
|
|
- goto AFE_AUD_ASM_H_ERR;
|
|
|
- }
|
|
|
-
|
|
|
- /* Set MT2701_AUD_ASM_M_SEL to MT2701_AUD_UNIVPLL2_D4 */
|
|
|
- ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_ASM_M_SEL]);
|
|
|
- if (ret) {
|
|
|
- dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
|
|
|
- __func__, aud_clks[MT2701_AUD_ASM_M_SEL], ret);
|
|
|
- goto AFE_AUD_ASM_M_ERR;
|
|
|
+ dev_err(afe->dev, "failed to enable audio system %d\n", ret);
|
|
|
+ return ret;
|
|
|
}
|
|
|
|
|
|
- ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_ASM_M_SEL],
|
|
|
- afe_priv->clocks[MT2701_AUD_UNIVPLL2_D4]);
|
|
|
- if (ret) {
|
|
|
- dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__,
|
|
|
- aud_clks[MT2701_AUD_ASM_M_SEL],
|
|
|
- aud_clks[MT2701_AUD_UNIVPLL2_D4], ret);
|
|
|
- goto AFE_AUD_ASM_M_ERR;
|
|
|
- }
|
|
|
+ regmap_update_bits(afe->regmap, ASYS_TOP_CON,
|
|
|
+ ASYS_TOP_CON_ASYS_TIMING_ON,
|
|
|
+ ASYS_TOP_CON_ASYS_TIMING_ON);
|
|
|
+ regmap_update_bits(afe->regmap, AFE_DAC_CON0,
|
|
|
+ AFE_DAC_CON0_AFE_ON,
|
|
|
+ AFE_DAC_CON0_AFE_ON);
|
|
|
|
|
|
- regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
|
|
|
- AUDIO_TOP_CON0_PDN_AFE, 0);
|
|
|
- regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
|
|
|
- AUDIO_TOP_CON0_PDN_APLL_CK, 0);
|
|
|
- regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
|
|
|
- AUDIO_TOP_CON4_PDN_A1SYS, 0);
|
|
|
- regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
|
|
|
- AUDIO_TOP_CON4_PDN_A2SYS, 0);
|
|
|
- regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
|
|
|
- AUDIO_TOP_CON4_PDN_AFE_CONN, 0);
|
|
|
+ /* Configure ASRC */
|
|
|
+ regmap_write(afe->regmap, PWR1_ASM_CON1, PWR1_ASM_CON1_INIT_VAL);
|
|
|
+ regmap_write(afe->regmap, PWR2_ASM_CON1, PWR2_ASM_CON1_INIT_VAL);
|
|
|
|
|
|
return 0;
|
|
|
-
|
|
|
-AFE_AUD_ASM_M_ERR:
|
|
|
- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_ASM_M_SEL]);
|
|
|
-AFE_AUD_ASM_H_ERR:
|
|
|
- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_ASM_H_SEL]);
|
|
|
-AFE_AUD_AUDINTBUS_ERR:
|
|
|
- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUDINTBUS]);
|
|
|
-AFE_AUD_INFRA_ERR:
|
|
|
- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
|
|
|
-
|
|
|
- return ret;
|
|
|
}
|
|
|
|
|
|
-void mt2701_turn_off_afe_clock(struct mtk_base_afe *afe)
|
|
|
+int mt2701_afe_disable_clock(struct mtk_base_afe *afe)
|
|
|
{
|
|
|
- struct mt2701_afe_private *afe_priv = afe->platform_priv;
|
|
|
+ regmap_update_bits(afe->regmap, ASYS_TOP_CON,
|
|
|
+ ASYS_TOP_CON_ASYS_TIMING_ON, 0);
|
|
|
+ regmap_update_bits(afe->regmap, AFE_DAC_CON0,
|
|
|
+ AFE_DAC_CON0_AFE_ON, 0);
|
|
|
+
|
|
|
+ mt2701_afe_disable_audsys(afe);
|
|
|
|
|
|
- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
|
|
|
-
|
|
|
- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUDINTBUS]);
|
|
|
- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_ASM_H_SEL]);
|
|
|
- clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_ASM_M_SEL]);
|
|
|
-
|
|
|
- regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
|
|
|
- AUDIO_TOP_CON0_PDN_AFE, AUDIO_TOP_CON0_PDN_AFE);
|
|
|
- regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
|
|
|
- AUDIO_TOP_CON0_PDN_APLL_CK,
|
|
|
- AUDIO_TOP_CON0_PDN_APLL_CK);
|
|
|
- regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
|
|
|
- AUDIO_TOP_CON4_PDN_A1SYS,
|
|
|
- AUDIO_TOP_CON4_PDN_A1SYS);
|
|
|
- regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
|
|
|
- AUDIO_TOP_CON4_PDN_A2SYS,
|
|
|
- AUDIO_TOP_CON4_PDN_A2SYS);
|
|
|
- regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
|
|
|
- AUDIO_TOP_CON4_PDN_AFE_CONN,
|
|
|
- AUDIO_TOP_CON4_PDN_AFE_CONN);
|
|
|
+ return 0;
|
|
|
}
|
|
|
|
|
|
void mt2701_mclk_configuration(struct mtk_base_afe *afe, int id, int domain,
|
|
|
int mclk)
|
|
|
{
|
|
|
- struct mt2701_afe_private *afe_priv = afe->platform_priv;
|
|
|
+ struct mt2701_afe_private *priv = afe->platform_priv;
|
|
|
+ struct mt2701_i2s_path *i2s_path = &priv->i2s_path[id];
|
|
|
int ret;
|
|
|
- int aud_src_div_id = MT2701_AUD_AUD_K1_SRC_DIV + id;
|
|
|
- int aud_src_clk_id = MT2701_AUD_AUD_K1_SRC_SEL + id;
|
|
|
|
|
|
- /* Set MCLK Kx_SRC_SEL(domain) */
|
|
|
- ret = clk_prepare_enable(afe_priv->clocks[aud_src_clk_id]);
|
|
|
- if (ret)
|
|
|
- dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
|
|
|
- __func__, aud_clks[aud_src_clk_id], ret);
|
|
|
-
|
|
|
- if (domain == 0) {
|
|
|
- ret = clk_set_parent(afe_priv->clocks[aud_src_clk_id],
|
|
|
- afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL]);
|
|
|
- if (ret)
|
|
|
- dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
|
|
|
- __func__, aud_clks[aud_src_clk_id],
|
|
|
- aud_clks[MT2701_AUD_AUD_MUX1_SEL], ret);
|
|
|
- } else {
|
|
|
- ret = clk_set_parent(afe_priv->clocks[aud_src_clk_id],
|
|
|
- afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL]);
|
|
|
- if (ret)
|
|
|
- dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
|
|
|
- __func__, aud_clks[aud_src_clk_id],
|
|
|
- aud_clks[MT2701_AUD_AUD_MUX2_SEL], ret);
|
|
|
- }
|
|
|
- clk_disable_unprepare(afe_priv->clocks[aud_src_clk_id]);
|
|
|
+ /* Set mclk source */
|
|
|
+ if (domain == 0)
|
|
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+ ret = clk_set_parent(i2s_path->sel_ck,
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+ priv->base_ck[MT2701_TOP_AUD_MCLK_SRC0]);
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+ else
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+ ret = clk_set_parent(i2s_path->sel_ck,
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+ priv->base_ck[MT2701_TOP_AUD_MCLK_SRC1]);
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- /* Set MCLK Kx_SRC_DIV(divider) */
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- ret = clk_prepare_enable(afe_priv->clocks[aud_src_div_id]);
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if (ret)
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- dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
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- __func__, aud_clks[aud_src_div_id], ret);
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+ dev_err(afe->dev, "failed to set domain%d mclk source %d\n",
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+ domain, ret);
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|
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- ret = clk_set_rate(afe_priv->clocks[aud_src_div_id], mclk);
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+ /* Set mclk divider */
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+ ret = clk_set_rate(i2s_path->div_ck, mclk);
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if (ret)
|
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- dev_err(afe->dev, "%s clk_set_rate %s-%d fail %d\n", __func__,
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- aud_clks[aud_src_div_id], mclk, ret);
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- clk_disable_unprepare(afe_priv->clocks[aud_src_div_id]);
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+ dev_err(afe->dev, "failed to set mclk divider %d\n", ret);
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}
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|
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-
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-MODULE_DESCRIPTION("MT2701 afe clock control");
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-MODULE_AUTHOR("Garlic Tseng <garlic.tseng@mediatek.com>");
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-MODULE_LICENSE("GPL v2");
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Mark Brown
7 years ago