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@@ -285,6 +285,36 @@ uint64_t get_vmem_size(struct kgd_dev *kgd)
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return adev->mc.real_vram_size;
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}
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+void get_local_mem_info(struct kgd_dev *kgd,
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+ struct kfd_local_mem_info *mem_info)
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+{
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+ struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
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+ uint64_t address_mask = adev->dev->dma_mask ? ~*adev->dev->dma_mask :
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+ ~((1ULL << 32) - 1);
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+ resource_size_t aper_limit = adev->mc.aper_base + adev->mc.aper_size;
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+
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+ memset(mem_info, 0, sizeof(*mem_info));
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+ if (!(adev->mc.aper_base & address_mask || aper_limit & address_mask)) {
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+ mem_info->local_mem_size_public = adev->mc.visible_vram_size;
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+ mem_info->local_mem_size_private = adev->mc.real_vram_size -
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+ adev->mc.visible_vram_size;
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+ } else {
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+ mem_info->local_mem_size_public = 0;
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+ mem_info->local_mem_size_private = adev->mc.real_vram_size;
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+ }
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+ mem_info->vram_width = adev->mc.vram_width;
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+
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+ pr_debug("Address base: 0x%llx limit 0x%llx public 0x%llx private 0x%llx\n",
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+ adev->mc.aper_base, aper_limit,
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+ mem_info->local_mem_size_public,
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+ mem_info->local_mem_size_private);
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+
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+ if (amdgpu_sriov_vf(adev))
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+ mem_info->mem_clk_max = adev->clock.default_mclk / 100;
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+ else
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+ mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100;
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+}
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+
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uint64_t get_gpu_clock_counter(struct kgd_dev *kgd)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
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