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@@ -225,13 +225,13 @@ static void b43_nphy_rf_ctl_override_one_to_many(struct b43_wldev *dev,
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b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 1);
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b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 1);
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b43_nphy_rf_ctl_override_rev7(dev, 0x1, value, core, off, 1);
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b43_nphy_rf_ctl_override_rev7(dev, 0x1, value, core, off, 1);
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b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 2);
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b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 2);
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- b43_nphy_rf_ctl_override_rev7(dev, 0x0800, value, core, off, 1);
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+ b43_nphy_rf_ctl_override_rev7(dev, 0x0800, 0, core, off, 1);
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break;
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break;
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case N_RF_CTL_OVER_CMD_TX_PU:
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case N_RF_CTL_OVER_CMD_TX_PU:
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b43_nphy_rf_ctl_override_rev7(dev, 0x4, value, core, off, 0);
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b43_nphy_rf_ctl_override_rev7(dev, 0x4, value, core, off, 0);
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b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 1);
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b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 1);
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b43_nphy_rf_ctl_override_rev7(dev, 0x1, value, core, off, 2);
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b43_nphy_rf_ctl_override_rev7(dev, 0x1, value, core, off, 2);
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- b43_nphy_rf_ctl_override_rev7(dev, 0x0800, value, core, off, 1);
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+ b43_nphy_rf_ctl_override_rev7(dev, 0x0800, 1, core, off, 1);
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break;
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break;
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case N_RF_CTL_OVER_CMD_RX_GAIN:
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case N_RF_CTL_OVER_CMD_RX_GAIN:
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tmp = value & 0xFF;
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tmp = value & 0xFF;
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@@ -343,6 +343,7 @@ static void b43_nphy_rf_ctl_intc_override_rev7(struct b43_wldev *dev,
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switch (intc_override) {
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switch (intc_override) {
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case N_INTC_OVERRIDE_OFF:
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case N_INTC_OVERRIDE_OFF:
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b43_phy_write(dev, reg, 0);
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b43_phy_write(dev, reg, 0);
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+ b43_phy_mask(dev, 0x2ff, ~0x2000);
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b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
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b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
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break;
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break;
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case N_INTC_OVERRIDE_TRSW:
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case N_INTC_OVERRIDE_TRSW:
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@@ -1596,7 +1597,7 @@ static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
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bool lpf_bw3, lpf_bw4;
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bool lpf_bw3, lpf_bw4;
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lpf_bw3 = b43_phy_read(dev, B43_NPHY_REV7_RF_CTL_OVER3) & 0x80;
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lpf_bw3 = b43_phy_read(dev, B43_NPHY_REV7_RF_CTL_OVER3) & 0x80;
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- lpf_bw4 = b43_phy_read(dev, B43_NPHY_REV7_RF_CTL_OVER3) & 0x80;
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+ lpf_bw4 = b43_phy_read(dev, B43_NPHY_REV7_RF_CTL_OVER4) & 0x80;
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if (lpf_bw3 || lpf_bw4) {
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if (lpf_bw3 || lpf_bw4) {
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/* TODO */
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/* TODO */
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@@ -2117,7 +2118,7 @@ static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
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N_RF_CTL_OVER_CMD_RX_PU,
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N_RF_CTL_OVER_CMD_RX_PU,
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1, 0, false);
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1, 0, false);
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b43_nphy_rf_ctl_override_rev7(dev, 0x80, 1, 0, false, 0);
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b43_nphy_rf_ctl_override_rev7(dev, 0x80, 1, 0, false, 0);
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- b43_nphy_rf_ctl_override_rev7(dev, 0x80, 1, 0, false, 0);
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+ b43_nphy_rf_ctl_override_rev7(dev, 0x40, 1, 0, false, 0);
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if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
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if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
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b43_nphy_rf_ctl_override_rev7(dev, 0x20, 0, 0, false,
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b43_nphy_rf_ctl_override_rev7(dev, 0x20, 0, 0, false,
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0);
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0);
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@@ -2708,25 +2709,39 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
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struct ssb_sprom *sprom = dev->dev->bus_sprom;
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struct ssb_sprom *sprom = dev->dev->bus_sprom;
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struct b43_phy *phy = &dev->phy;
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struct b43_phy *phy = &dev->phy;
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+ /* TX to RX */
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+ u8 tx2rx_events[7] = { 4, 3, 5, 2, 1, 8, 31, };
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+ u8 tx2rx_delays[7] = { 8, 4, 4, 4, 4, 6, 1, };
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+ /* RX to TX */
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u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
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u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
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0x1F };
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0x1F };
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u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
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u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
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- u16 ntab7_15e_16e[] = { 0x10f, 0x10f };
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+ static const u16 ntab7_15e_16e[] = { 0, 0x10f, 0x10f };
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u8 ntab7_138_146[] = { 0x11, 0x11 };
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u8 ntab7_138_146[] = { 0x11, 0x11 };
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u8 ntab7_133[] = { 0x77, 0x11, 0x11 };
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u8 ntab7_133[] = { 0x77, 0x11, 0x11 };
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- u16 lpf_20, lpf_40, lpf_11b;
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- u16 bcap_val, bcap_val_11b, bcap_val_11n_20, bcap_val_11n_40;
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- u16 scap_val, scap_val_11b, scap_val_11n_20, scap_val_11n_40;
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+ u16 lpf_ofdm_20mhz[2], lpf_ofdm_40mhz[2], lpf_11b[2];
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+ u16 bcap_val;
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+ s16 bcap_val_11b[2], bcap_val_11n_20[2], bcap_val_11n_40[2];
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+ u16 scap_val;
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+ s16 scap_val_11b[2], scap_val_11n_20[2], scap_val_11n_40[2];
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bool rccal_ovrd = false;
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bool rccal_ovrd = false;
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- u16 rx2tx_lut_20_11b, rx2tx_lut_20_11n, rx2tx_lut_40_11n;
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u16 bias, conv, filt;
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u16 bias, conv, filt;
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+ u32 noise_tbl[2];
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+
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u32 tmp32;
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u32 tmp32;
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u8 core;
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u8 core;
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+ b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
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+ b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01b3);
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+ b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
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+ b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016e);
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+ b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00cd);
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+ b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
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+
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if (phy->rev == 7) {
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if (phy->rev == 7) {
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b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 0x10);
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b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 0x10);
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b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0xFF80, 0x0020);
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b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0xFF80, 0x0020);
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@@ -2746,11 +2761,18 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
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b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0xFF80, 0x0040);
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b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0xFF80, 0x0040);
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b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000);
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b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000);
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}
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}
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- if (phy->rev <= 8) {
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+
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+ if (phy->rev >= 16) {
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+ b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x7ff);
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+ b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x7ff);
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+ } else if (phy->rev <= 8) {
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b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1B0);
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b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1B0);
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b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1B0);
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b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1B0);
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}
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}
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- if (phy->rev >= 8)
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+
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+ if (phy->rev >= 16)
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+ b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0xa0);
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+ else if (phy->rev >= 8)
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b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72);
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b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72);
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b43_ntab_write(dev, B43_NTAB16(8, 0x00), 2);
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b43_ntab_write(dev, B43_NTAB16(8, 0x00), 2);
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@@ -2758,9 +2780,11 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
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tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
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tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
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tmp32 &= 0xffffff;
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tmp32 &= 0xffffff;
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b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
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b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
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- b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x15e), 2, ntab7_15e_16e);
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- b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x16e), 2, ntab7_15e_16e);
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+ b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x15d), 3, ntab7_15e_16e);
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+ b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x16d), 3, ntab7_15e_16e);
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+ b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
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+ ARRAY_SIZE(tx2rx_events));
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if (b43_nphy_ipa(dev))
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if (b43_nphy_ipa(dev))
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b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
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b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
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rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
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rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
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@@ -2768,84 +2792,176 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
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b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_0, 0x3FFF, 0x4000);
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b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_0, 0x3FFF, 0x4000);
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b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_1, 0x3FFF, 0x4000);
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b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_1, 0x3FFF, 0x4000);
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- lpf_20 = b43_nphy_read_lpf_ctl(dev, 0x154);
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- lpf_40 = b43_nphy_read_lpf_ctl(dev, 0x159);
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- lpf_11b = b43_nphy_read_lpf_ctl(dev, 0x152);
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+ for (core = 0; core < 2; core++) {
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+ lpf_ofdm_20mhz[core] = b43_nphy_read_lpf_ctl(dev, 0x154 + core * 0x10);
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+ lpf_ofdm_40mhz[core] = b43_nphy_read_lpf_ctl(dev, 0x159 + core * 0x10);
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+ lpf_11b[core] = b43_nphy_read_lpf_ctl(dev, 0x152 + core * 0x10);
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+ }
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+
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+ bcap_val = b43_radio_read(dev, R2057_RCCAL_BCAP_VAL);
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+ scap_val = b43_radio_read(dev, R2057_RCCAL_SCAP_VAL);
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+
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if (b43_nphy_ipa(dev)) {
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if (b43_nphy_ipa(dev)) {
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- if ((phy->radio_rev == 5 && b43_is_40mhz(dev)) ||
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- phy->radio_rev == 7 || phy->radio_rev == 8) {
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- bcap_val = b43_radio_read(dev, 0x16b);
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- scap_val = b43_radio_read(dev, 0x16a);
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- scap_val_11b = scap_val;
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- bcap_val_11b = bcap_val;
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- if (phy->radio_rev == 5 && b43_is_40mhz(dev)) {
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- scap_val_11n_20 = scap_val;
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- bcap_val_11n_20 = bcap_val;
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- scap_val_11n_40 = bcap_val_11n_40 = 0xc;
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+ bool ghz2 = b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ;
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+
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+ switch (phy->radio_rev) {
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+ case 5:
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+ /* Check radio version (to be 0) by PHY rev for now */
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+ if (phy->rev == 8 && b43_is_40mhz(dev)) {
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+ for (core = 0; core < 2; core++) {
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+ scap_val_11b[core] = scap_val;
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+ bcap_val_11b[core] = bcap_val;
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+ scap_val_11n_20[core] = scap_val;
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+ bcap_val_11n_20[core] = bcap_val;
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+ scap_val_11n_40[core] = 0xc;
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+ bcap_val_11n_40[core] = 0xc;
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+ }
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+
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rccal_ovrd = true;
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rccal_ovrd = true;
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- } else { /* Rev 7/8 */
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- lpf_20 = 4;
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- lpf_11b = 1;
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+ }
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+ if (phy->rev == 9) {
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+ /* TODO: Radio version 1 (e.g. BCM5357B0) */
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+ }
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+ break;
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+ case 7:
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+ case 8:
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+ for (core = 0; core < 2; core++) {
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+ scap_val_11b[core] = scap_val;
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+ bcap_val_11b[core] = bcap_val;
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+ lpf_ofdm_20mhz[core] = 4;
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+ lpf_11b[core] = 1;
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if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
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if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
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- scap_val_11n_20 = 0xc;
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- bcap_val_11n_20 = 0xc;
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- scap_val_11n_40 = 0xa;
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- bcap_val_11n_40 = 0xa;
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+ scap_val_11n_20[core] = 0xc;
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+ bcap_val_11n_20[core] = 0xc;
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+ scap_val_11n_40[core] = 0xa;
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+ bcap_val_11n_40[core] = 0xa;
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} else {
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} else {
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- scap_val_11n_20 = 0x14;
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- bcap_val_11n_20 = 0x14;
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- scap_val_11n_40 = 0xf;
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- bcap_val_11n_40 = 0xf;
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+ scap_val_11n_20[core] = 0x14;
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+ bcap_val_11n_20[core] = 0x14;
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+ scap_val_11n_40[core] = 0xf;
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+ bcap_val_11n_40[core] = 0xf;
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}
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}
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- rccal_ovrd = true;
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}
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}
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+
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+ rccal_ovrd = true;
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+ break;
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+ case 9:
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+ for (core = 0; core < 2; core++) {
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+ bcap_val_11b[core] = bcap_val;
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+ scap_val_11b[core] = scap_val;
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+ lpf_11b[core] = 1;
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+
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+ if (ghz2) {
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+ bcap_val_11n_20[core] = bcap_val + 13;
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+ scap_val_11n_20[core] = scap_val + 15;
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+ } else {
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+ bcap_val_11n_20[core] = bcap_val + 14;
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+ scap_val_11n_20[core] = scap_val + 15;
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+ }
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+ lpf_ofdm_20mhz[core] = 4;
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+
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+ if (ghz2) {
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|
|
+ bcap_val_11n_40[core] = bcap_val - 7;
|
|
|
|
+ scap_val_11n_40[core] = scap_val - 5;
|
|
|
|
+ } else {
|
|
|
|
+ bcap_val_11n_40[core] = bcap_val + 2;
|
|
|
|
+ scap_val_11n_40[core] = scap_val + 4;
|
|
|
|
+ }
|
|
|
|
+ lpf_ofdm_40mhz[core] = 4;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ rccal_ovrd = true;
|
|
|
|
+ break;
|
|
|
|
+ case 14:
|
|
|
|
+ for (core = 0; core < 2; core++) {
|
|
|
|
+ bcap_val_11b[core] = bcap_val;
|
|
|
|
+ scap_val_11b[core] = scap_val;
|
|
|
|
+ lpf_11b[core] = 1;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ bcap_val_11n_20[0] = bcap_val + 20;
|
|
|
|
+ scap_val_11n_20[0] = scap_val + 20;
|
|
|
|
+ lpf_ofdm_20mhz[0] = 3;
|
|
|
|
+
|
|
|
|
+ bcap_val_11n_20[1] = bcap_val + 16;
|
|
|
|
+ scap_val_11n_20[1] = scap_val + 16;
|
|
|
|
+ lpf_ofdm_20mhz[1] = 3;
|
|
|
|
+
|
|
|
|
+ bcap_val_11n_40[0] = bcap_val + 20;
|
|
|
|
+ scap_val_11n_40[0] = scap_val + 20;
|
|
|
|
+ lpf_ofdm_40mhz[0] = 4;
|
|
|
|
+
|
|
|
|
+ bcap_val_11n_40[1] = bcap_val + 10;
|
|
|
|
+ scap_val_11n_40[1] = scap_val + 10;
|
|
|
|
+ lpf_ofdm_40mhz[1] = 4;
|
|
|
|
+
|
|
|
|
+ rccal_ovrd = true;
|
|
|
|
+ break;
|
|
}
|
|
}
|
|
} else {
|
|
} else {
|
|
if (phy->radio_rev == 5) {
|
|
if (phy->radio_rev == 5) {
|
|
- lpf_20 = 1;
|
|
|
|
- lpf_40 = 3;
|
|
|
|
- bcap_val = b43_radio_read(dev, 0x16b);
|
|
|
|
- scap_val = b43_radio_read(dev, 0x16a);
|
|
|
|
- scap_val_11b = scap_val;
|
|
|
|
- bcap_val_11b = bcap_val;
|
|
|
|
- scap_val_11n_20 = 0x11;
|
|
|
|
- scap_val_11n_40 = 0x11;
|
|
|
|
- bcap_val_11n_20 = 0x13;
|
|
|
|
- bcap_val_11n_40 = 0x13;
|
|
|
|
|
|
+ for (core = 0; core < 2; core++) {
|
|
|
|
+ lpf_ofdm_20mhz[core] = 1;
|
|
|
|
+ lpf_ofdm_40mhz[core] = 3;
|
|
|
|
+ scap_val_11b[core] = scap_val;
|
|
|
|
+ bcap_val_11b[core] = bcap_val;
|
|
|
|
+ scap_val_11n_20[core] = 0x11;
|
|
|
|
+ scap_val_11n_40[core] = 0x11;
|
|
|
|
+ bcap_val_11n_20[core] = 0x13;
|
|
|
|
+ bcap_val_11n_40[core] = 0x13;
|
|
|
|
+ }
|
|
|
|
+
|
|
rccal_ovrd = true;
|
|
rccal_ovrd = true;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
if (rccal_ovrd) {
|
|
if (rccal_ovrd) {
|
|
- rx2tx_lut_20_11b = (bcap_val_11b << 8) |
|
|
|
|
- (scap_val_11b << 3) |
|
|
|
|
- lpf_11b;
|
|
|
|
- rx2tx_lut_20_11n = (bcap_val_11n_20 << 8) |
|
|
|
|
- (scap_val_11n_20 << 3) |
|
|
|
|
- lpf_20;
|
|
|
|
- rx2tx_lut_40_11n = (bcap_val_11n_40 << 8) |
|
|
|
|
- (scap_val_11n_40 << 3) |
|
|
|
|
- lpf_40;
|
|
|
|
|
|
+ u16 rx2tx_lut_20_11b[2], rx2tx_lut_20_11n[2], rx2tx_lut_40_11n[2];
|
|
|
|
+ u8 rx2tx_lut_extra = 1;
|
|
|
|
+
|
|
|
|
+ for (core = 0; core < 2; core++) {
|
|
|
|
+ bcap_val_11b[core] = clamp_val(bcap_val_11b[core], 0, 0x1f);
|
|
|
|
+ scap_val_11b[core] = clamp_val(scap_val_11b[core], 0, 0x1f);
|
|
|
|
+ bcap_val_11n_20[core] = clamp_val(bcap_val_11n_20[core], 0, 0x1f);
|
|
|
|
+ scap_val_11n_20[core] = clamp_val(scap_val_11n_20[core], 0, 0x1f);
|
|
|
|
+ bcap_val_11n_40[core] = clamp_val(bcap_val_11n_40[core], 0, 0x1f);
|
|
|
|
+ scap_val_11n_40[core] = clamp_val(scap_val_11n_40[core], 0, 0x1f);
|
|
|
|
+
|
|
|
|
+ rx2tx_lut_20_11b[core] = (rx2tx_lut_extra << 13) |
|
|
|
|
+ (bcap_val_11b[core] << 8) |
|
|
|
|
+ (scap_val_11b[core] << 3) |
|
|
|
|
+ lpf_11b[core];
|
|
|
|
+ rx2tx_lut_20_11n[core] = (rx2tx_lut_extra << 13) |
|
|
|
|
+ (bcap_val_11n_20[core] << 8) |
|
|
|
|
+ (scap_val_11n_20[core] << 3) |
|
|
|
|
+ lpf_ofdm_20mhz[core];
|
|
|
|
+ rx2tx_lut_40_11n[core] = (rx2tx_lut_extra << 13) |
|
|
|
|
+ (bcap_val_11n_40[core] << 8) |
|
|
|
|
+ (scap_val_11n_40[core] << 3) |
|
|
|
|
+ lpf_ofdm_40mhz[core];
|
|
|
|
+ }
|
|
|
|
+
|
|
for (core = 0; core < 2; core++) {
|
|
for (core = 0; core < 2; core++) {
|
|
b43_ntab_write(dev, B43_NTAB16(7, 0x152 + core * 16),
|
|
b43_ntab_write(dev, B43_NTAB16(7, 0x152 + core * 16),
|
|
- rx2tx_lut_20_11b);
|
|
|
|
|
|
+ rx2tx_lut_20_11b[core]);
|
|
b43_ntab_write(dev, B43_NTAB16(7, 0x153 + core * 16),
|
|
b43_ntab_write(dev, B43_NTAB16(7, 0x153 + core * 16),
|
|
- rx2tx_lut_20_11n);
|
|
|
|
|
|
+ rx2tx_lut_20_11n[core]);
|
|
b43_ntab_write(dev, B43_NTAB16(7, 0x154 + core * 16),
|
|
b43_ntab_write(dev, B43_NTAB16(7, 0x154 + core * 16),
|
|
- rx2tx_lut_20_11n);
|
|
|
|
|
|
+ rx2tx_lut_20_11n[core]);
|
|
b43_ntab_write(dev, B43_NTAB16(7, 0x155 + core * 16),
|
|
b43_ntab_write(dev, B43_NTAB16(7, 0x155 + core * 16),
|
|
- rx2tx_lut_40_11n);
|
|
|
|
|
|
+ rx2tx_lut_40_11n[core]);
|
|
b43_ntab_write(dev, B43_NTAB16(7, 0x156 + core * 16),
|
|
b43_ntab_write(dev, B43_NTAB16(7, 0x156 + core * 16),
|
|
- rx2tx_lut_40_11n);
|
|
|
|
|
|
+ rx2tx_lut_40_11n[core]);
|
|
b43_ntab_write(dev, B43_NTAB16(7, 0x157 + core * 16),
|
|
b43_ntab_write(dev, B43_NTAB16(7, 0x157 + core * 16),
|
|
- rx2tx_lut_40_11n);
|
|
|
|
|
|
+ rx2tx_lut_40_11n[core]);
|
|
b43_ntab_write(dev, B43_NTAB16(7, 0x158 + core * 16),
|
|
b43_ntab_write(dev, B43_NTAB16(7, 0x158 + core * 16),
|
|
- rx2tx_lut_40_11n);
|
|
|
|
|
|
+ rx2tx_lut_40_11n[core]);
|
|
b43_ntab_write(dev, B43_NTAB16(7, 0x159 + core * 16),
|
|
b43_ntab_write(dev, B43_NTAB16(7, 0x159 + core * 16),
|
|
- rx2tx_lut_40_11n);
|
|
|
|
|
|
+ rx2tx_lut_40_11n[core]);
|
|
}
|
|
}
|
|
- b43_nphy_rf_ctl_override_rev7(dev, 16, 1, 3, false, 2);
|
|
|
|
}
|
|
}
|
|
|
|
+
|
|
b43_phy_write(dev, 0x32F, 0x3);
|
|
b43_phy_write(dev, 0x32F, 0x3);
|
|
|
|
+
|
|
if (phy->radio_rev == 4 || phy->radio_rev == 6)
|
|
if (phy->radio_rev == 4 || phy->radio_rev == 6)
|
|
b43_nphy_rf_ctl_override_rev7(dev, 4, 1, 3, false, 0);
|
|
b43_nphy_rf_ctl_override_rev7(dev, 4, 1, 3, false, 0);
|
|
|
|
|
|
@@ -2893,7 +3009,8 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
|
|
0x7f);
|
|
0x7f);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
- if (phy->radio_rev == 3) {
|
|
|
|
|
|
+ switch (phy->radio_rev) {
|
|
|
|
+ case 3:
|
|
for (core = 0; core < 2; core++) {
|
|
for (core = 0; core < 2; core++) {
|
|
if (core == 0) {
|
|
if (core == 0) {
|
|
b43_radio_write(dev, 0x64,
|
|
b43_radio_write(dev, 0x64,
|
|
@@ -2919,7 +3036,9 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
|
|
0x3E);
|
|
0x3E);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
- } else if (phy->radio_rev == 7 || phy->radio_rev == 8) {
|
|
|
|
|
|
+ break;
|
|
|
|
+ case 7:
|
|
|
|
+ case 8:
|
|
if (!b43_is_40mhz(dev)) {
|
|
if (!b43_is_40mhz(dev)) {
|
|
b43_radio_write(dev, 0x5F, 0x14);
|
|
b43_radio_write(dev, 0x5F, 0x14);
|
|
b43_radio_write(dev, 0xE8, 0x12);
|
|
b43_radio_write(dev, 0xE8, 0x12);
|
|
@@ -2927,6 +3046,21 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
|
|
b43_radio_write(dev, 0x5F, 0x16);
|
|
b43_radio_write(dev, 0x5F, 0x16);
|
|
b43_radio_write(dev, 0xE8, 0x16);
|
|
b43_radio_write(dev, 0xE8, 0x16);
|
|
}
|
|
}
|
|
|
|
+ break;
|
|
|
|
+ case 14:
|
|
|
|
+ for (core = 0; core < 2; core++) {
|
|
|
|
+ int o = core ? 0x85 : 0;
|
|
|
|
+
|
|
|
|
+ b43_radio_write(dev, o + R2057_IPA2G_CASCONV_CORE0, 0x13);
|
|
|
|
+ b43_radio_write(dev, o + R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, 0x21);
|
|
|
|
+ b43_radio_write(dev, o + R2057_IPA2G_BIAS_FILTER_CORE0, 0xff);
|
|
|
|
+ b43_radio_write(dev, o + R2057_PAD2G_IDACS_CORE0, 0x88);
|
|
|
|
+ b43_radio_write(dev, o + R2057_PAD2G_TUNE_PUS_CORE0, 0x23);
|
|
|
|
+ b43_radio_write(dev, o + R2057_IPA2G_IMAIN_CORE0, 0x16);
|
|
|
|
+ b43_radio_write(dev, o + R2057_PAD_BIAS_FILTER_BWS_CORE0, 0x3e);
|
|
|
|
+ b43_radio_write(dev, o + R2057_BACKUP1_CORE0, 0x10);
|
|
|
|
+ }
|
|
|
|
+ break;
|
|
}
|
|
}
|
|
} else {
|
|
} else {
|
|
u16 freq = phy->chandef->chan->center_freq;
|
|
u16 freq = phy->chandef->chan->center_freq;
|
|
@@ -2974,8 +3108,8 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
|
|
b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x1);
|
|
b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x1);
|
|
b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x1);
|
|
b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x1);
|
|
b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x1);
|
|
b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x1);
|
|
- b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
|
|
|
|
- b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
|
|
|
|
|
|
+ b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0);
|
|
|
|
+ b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0);
|
|
|
|
|
|
b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x4);
|
|
b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x4);
|
|
b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x4);
|
|
b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x4);
|
|
@@ -2986,20 +3120,20 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
|
|
b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, 0x2);
|
|
b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, 0x2);
|
|
|
|
|
|
b43_ntab_write(dev, B43_NTAB32(16, 0x100), 20);
|
|
b43_ntab_write(dev, B43_NTAB32(16, 0x100), 20);
|
|
- b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x138), 2, ntab7_138_146);
|
|
|
|
|
|
+ b43_ntab_write_bulk(dev, B43_NTAB8(7, 0x138), 2, ntab7_138_146);
|
|
b43_ntab_write(dev, B43_NTAB16(7, 0x141), 0x77);
|
|
b43_ntab_write(dev, B43_NTAB16(7, 0x141), 0x77);
|
|
- b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x133), 3, ntab7_133);
|
|
|
|
- b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x146), 2, ntab7_138_146);
|
|
|
|
|
|
+ b43_ntab_write_bulk(dev, B43_NTAB8(7, 0x133), 3, ntab7_133);
|
|
|
|
+ b43_ntab_write_bulk(dev, B43_NTAB8(7, 0x146), 2, ntab7_138_146);
|
|
b43_ntab_write(dev, B43_NTAB16(7, 0x123), 0x77);
|
|
b43_ntab_write(dev, B43_NTAB16(7, 0x123), 0x77);
|
|
b43_ntab_write(dev, B43_NTAB16(7, 0x12A), 0x77);
|
|
b43_ntab_write(dev, B43_NTAB16(7, 0x12A), 0x77);
|
|
|
|
|
|
- if (!b43_is_40mhz(dev)) {
|
|
|
|
- b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x18D);
|
|
|
|
- b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x18D);
|
|
|
|
- } else {
|
|
|
|
- b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x14D);
|
|
|
|
- b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x14D);
|
|
|
|
- }
|
|
|
|
|
|
+ b43_ntab_read_bulk(dev, B43_NTAB32(16, 0x02), 1, noise_tbl);
|
|
|
|
+ noise_tbl[1] = b43_is_40mhz(dev) ? 0x14D : 0x18D;
|
|
|
|
+ b43_ntab_write_bulk(dev, B43_NTAB32(16, 0x02), 2, noise_tbl);
|
|
|
|
+
|
|
|
|
+ b43_ntab_read_bulk(dev, B43_NTAB32(16, 0x7E), 1, noise_tbl);
|
|
|
|
+ noise_tbl[1] = b43_is_40mhz(dev) ? 0x14D : 0x18D;
|
|
|
|
+ b43_ntab_write_bulk(dev, B43_NTAB32(16, 0x7E), 2, noise_tbl);
|
|
|
|
|
|
b43_nphy_gain_ctl_workarounds(dev);
|
|
b43_nphy_gain_ctl_workarounds(dev);
|
|
|
|
|
|
@@ -3410,7 +3544,7 @@ static void b43_nphy_stop_playback(struct b43_wldev *dev)
|
|
nphy->bb_mult_save = 0;
|
|
nphy->bb_mult_save = 0;
|
|
}
|
|
}
|
|
|
|
|
|
- if (phy->rev >= 7) {
|
|
|
|
|
|
+ if (phy->rev >= 7 && nphy->lpf_bw_overrode_for_sample_play) {
|
|
if (phy->rev >= 19)
|
|
if (phy->rev >= 19)
|
|
b43_nphy_rf_ctl_override_rev19(dev, 0x80, 0, 0, true,
|
|
b43_nphy_rf_ctl_override_rev19(dev, 0x80, 0, 0, true,
|
|
1);
|
|
1);
|
|
@@ -3823,15 +3957,16 @@ static void b43_nphy_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
|
|
u32 tmp;
|
|
u32 tmp;
|
|
s32 rssi[4] = { };
|
|
s32 rssi[4] = { };
|
|
|
|
|
|
- /* TODO: check if we can transmit */
|
|
|
|
|
|
+ if (phy->chandef->chan->flags & IEEE80211_CHAN_NO_IR)
|
|
|
|
+ return;
|
|
|
|
|
|
if (b43_nphy_ipa(dev))
|
|
if (b43_nphy_ipa(dev))
|
|
b43_nphy_ipa_internal_tssi_setup(dev);
|
|
b43_nphy_ipa_internal_tssi_setup(dev);
|
|
|
|
|
|
if (phy->rev >= 19)
|
|
if (phy->rev >= 19)
|
|
- b43_nphy_rf_ctl_override_rev19(dev, 0x2000, 0, 3, false, 0);
|
|
|
|
|
|
+ b43_nphy_rf_ctl_override_rev19(dev, 0x1000, 0, 3, false, 0);
|
|
else if (phy->rev >= 7)
|
|
else if (phy->rev >= 7)
|
|
- b43_nphy_rf_ctl_override_rev7(dev, 0x2000, 0, 3, false, 0);
|
|
|
|
|
|
+ b43_nphy_rf_ctl_override_rev7(dev, 0x1000, 0, 3, false, 0);
|
|
else if (phy->rev >= 3)
|
|
else if (phy->rev >= 3)
|
|
b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, false);
|
|
b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, false);
|
|
|
|
|
|
@@ -3844,9 +3979,9 @@ static void b43_nphy_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
|
|
b43_nphy_rssi_select(dev, 0, N_RSSI_W1);
|
|
b43_nphy_rssi_select(dev, 0, N_RSSI_W1);
|
|
|
|
|
|
if (phy->rev >= 19)
|
|
if (phy->rev >= 19)
|
|
- b43_nphy_rf_ctl_override_rev19(dev, 0x2000, 0, 3, true, 0);
|
|
|
|
|
|
+ b43_nphy_rf_ctl_override_rev19(dev, 0x1000, 0, 3, true, 0);
|
|
else if (phy->rev >= 7)
|
|
else if (phy->rev >= 7)
|
|
- b43_nphy_rf_ctl_override_rev7(dev, 0x2000, 0, 3, true, 0);
|
|
|
|
|
|
+ b43_nphy_rf_ctl_override_rev7(dev, 0x1000, 0, 3, true, 0);
|
|
else if (phy->rev >= 3)
|
|
else if (phy->rev >= 3)
|
|
b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, true);
|
|
b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, true);
|
|
|
|
|
|
@@ -4809,41 +4944,61 @@ static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
|
|
+static void b43_nphy_pa_set_tx_dig_filter(struct b43_wldev *dev, u16 offset,
|
|
|
|
+ const s16 *filter)
|
|
|
|
+{
|
|
|
|
+ int i;
|
|
|
|
+
|
|
|
|
+ offset = B43_PHY_N(offset);
|
|
|
|
+
|
|
|
|
+ for (i = 0; i < 15; i++, offset++)
|
|
|
|
+ b43_phy_write(dev, offset, filter[i]);
|
|
|
|
+}
|
|
|
|
+
|
|
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
|
|
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
|
|
static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
|
|
static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
|
|
{
|
|
{
|
|
- int i;
|
|
|
|
- for (i = 0; i < 15; i++)
|
|
|
|
- b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
|
|
|
|
- tbl_tx_filter_coef_rev4[2][i]);
|
|
|
|
|
|
+ b43_nphy_pa_set_tx_dig_filter(dev, 0x2C5,
|
|
|
|
+ tbl_tx_filter_coef_rev4[2]);
|
|
}
|
|
}
|
|
|
|
|
|
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
|
|
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
|
|
static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
|
|
static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
|
|
{
|
|
{
|
|
- int i, j;
|
|
|
|
/* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
|
|
/* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
|
|
static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
|
|
static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
|
|
|
|
+ static const s16 dig_filter_phy_rev16[] = {
|
|
|
|
+ -375, 136, -407, 208, -1527,
|
|
|
|
+ 956, 93, 186, 93, 230,
|
|
|
|
+ -44, 230, 201, -191, 201,
|
|
|
|
+ };
|
|
|
|
+ int i;
|
|
|
|
|
|
for (i = 0; i < 3; i++)
|
|
for (i = 0; i < 3; i++)
|
|
- for (j = 0; j < 15; j++)
|
|
|
|
- b43_phy_write(dev, B43_PHY_N(offset[i] + j),
|
|
|
|
- tbl_tx_filter_coef_rev4[i][j]);
|
|
|
|
|
|
+ b43_nphy_pa_set_tx_dig_filter(dev, offset[i],
|
|
|
|
+ tbl_tx_filter_coef_rev4[i]);
|
|
|
|
+
|
|
|
|
+ /* Verified with BCM43227 and BCM43228 */
|
|
|
|
+ if (dev->phy.rev == 16)
|
|
|
|
+ b43_nphy_pa_set_tx_dig_filter(dev, 0x186, dig_filter_phy_rev16);
|
|
|
|
+
|
|
|
|
+ if (dev->dev->chip_id == BCMA_CHIP_ID_BCM43217) {
|
|
|
|
+ b43_nphy_pa_set_tx_dig_filter(dev, 0x186, dig_filter_phy_rev16);
|
|
|
|
+ b43_nphy_pa_set_tx_dig_filter(dev, 0x195,
|
|
|
|
+ tbl_tx_filter_coef_rev4[1]);
|
|
|
|
+ }
|
|
|
|
|
|
if (b43_is_40mhz(dev)) {
|
|
if (b43_is_40mhz(dev)) {
|
|
- for (j = 0; j < 15; j++)
|
|
|
|
- b43_phy_write(dev, B43_PHY_N(offset[0] + j),
|
|
|
|
- tbl_tx_filter_coef_rev4[3][j]);
|
|
|
|
- } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
|
|
|
|
- for (j = 0; j < 15; j++)
|
|
|
|
- b43_phy_write(dev, B43_PHY_N(offset[0] + j),
|
|
|
|
- tbl_tx_filter_coef_rev4[5][j]);
|
|
|
|
- }
|
|
|
|
-
|
|
|
|
- if (dev->phy.channel == 14)
|
|
|
|
- for (j = 0; j < 15; j++)
|
|
|
|
- b43_phy_write(dev, B43_PHY_N(offset[0] + j),
|
|
|
|
- tbl_tx_filter_coef_rev4[6][j]);
|
|
|
|
|
|
+ b43_nphy_pa_set_tx_dig_filter(dev, 0x186,
|
|
|
|
+ tbl_tx_filter_coef_rev4[3]);
|
|
|
|
+ } else {
|
|
|
|
+ if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
|
|
|
|
+ b43_nphy_pa_set_tx_dig_filter(dev, 0x186,
|
|
|
|
+ tbl_tx_filter_coef_rev4[5]);
|
|
|
|
+ if (dev->phy.channel == 14)
|
|
|
|
+ b43_nphy_pa_set_tx_dig_filter(dev, 0x186,
|
|
|
|
+ tbl_tx_filter_coef_rev4[6]);
|
|
|
|
+ }
|
|
}
|
|
}
|
|
|
|
|
|
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
|
|
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
|