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@@ -1499,9 +1499,8 @@ EXPORT_SYMBOL(dw_dma_cyclic_free);
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int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
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{
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struct dw_dma *dw;
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- bool autocfg;
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+ bool autocfg = false;
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unsigned int dw_params;
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- unsigned int nr_channels;
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unsigned int max_blk_size = 0;
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int err;
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int i;
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@@ -1515,33 +1514,41 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
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pm_runtime_get_sync(chip->dev);
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- dw_params = dma_read_byaddr(chip->regs, DW_PARAMS);
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- autocfg = dw_params >> DW_PARAMS_EN & 0x1;
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+ if (!pdata) {
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+ dw_params = dma_read_byaddr(chip->regs, DW_PARAMS);
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+ dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params);
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- dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params);
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+ autocfg = dw_params >> DW_PARAMS_EN & 1;
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+ if (!autocfg) {
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+ err = -EINVAL;
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+ goto err_pdata;
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+ }
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- if (!pdata && autocfg) {
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pdata = devm_kzalloc(chip->dev, sizeof(*pdata), GFP_KERNEL);
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if (!pdata) {
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err = -ENOMEM;
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goto err_pdata;
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}
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+ /* Get hardware configuration parameters */
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+ pdata->nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 7) + 1;
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+ pdata->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
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+ for (i = 0; i < pdata->nr_masters; i++) {
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+ pdata->data_width[i] =
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+ (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
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+ }
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+ max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
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+
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/* Fill platform data with the default values */
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pdata->is_private = true;
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pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
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pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
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- } else if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) {
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+ } else if (pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) {
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err = -EINVAL;
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goto err_pdata;
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}
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- if (autocfg)
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- nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1;
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- else
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- nr_channels = pdata->nr_channels;
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-
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- dw->chan = devm_kcalloc(chip->dev, nr_channels, sizeof(*dw->chan),
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+ dw->chan = devm_kcalloc(chip->dev, pdata->nr_channels, sizeof(*dw->chan),
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GFP_KERNEL);
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if (!dw->chan) {
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err = -ENOMEM;
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@@ -1549,22 +1556,12 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
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}
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/* Get hardware configuration parameters */
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- if (autocfg) {
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- max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
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-
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- dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
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- for (i = 0; i < dw->nr_masters; i++) {
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- dw->data_width[i] =
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- (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
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- }
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- } else {
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- dw->nr_masters = pdata->nr_masters;
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- for (i = 0; i < dw->nr_masters; i++)
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- dw->data_width[i] = pdata->data_width[i];
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- }
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+ dw->nr_masters = pdata->nr_masters;
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+ for (i = 0; i < dw->nr_masters; i++)
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+ dw->data_width[i] = pdata->data_width[i];
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/* Calculate all channel mask before DMA setup */
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- dw->all_chan_mask = (1 << nr_channels) - 1;
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+ dw->all_chan_mask = (1 << pdata->nr_channels) - 1;
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/* Force dma off, just in case */
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dw_dma_off(dw);
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@@ -1589,7 +1586,7 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
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goto err_pdata;
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INIT_LIST_HEAD(&dw->dma.channels);
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- for (i = 0; i < nr_channels; i++) {
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+ for (i = 0; i < pdata->nr_channels; i++) {
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struct dw_dma_chan *dwc = &dw->chan[i];
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int r = nr_channels - i - 1;
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@@ -1603,7 +1600,7 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
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/* 7 is highest priority & 0 is lowest. */
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if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
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- dwc->priority = r;
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+ dwc->priority = pdata->nr_channels - i - 1;
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else
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dwc->priority = i;
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@@ -1687,7 +1684,7 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
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goto err_dma_register;
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dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n",
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- nr_channels);
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+ pdata->nr_channels);
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pm_runtime_put_sync_suspend(chip->dev);
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