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@@ -42,6 +42,7 @@
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#define REG_STEPCONFIG(n) (0x64 + ((n - 1) * 8))
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#define REG_STEPDELAY(n) (0x68 + ((n - 1) * 8))
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#define REG_FIFO0CNT 0xE4
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+#define REG_FIFO0THR 0xE8
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#define REG_FIFO1THR 0xF4
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#define REG_FIFO0 0x100
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#define REG_FIFO1 0x200
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@@ -55,6 +56,7 @@
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#define STPENB_STEPENB STEPENB(0x7FFF)
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/* IRQ enable */
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+#define IRQENB_FIFO0THRES BIT(2)
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#define IRQENB_FIFO1THRES BIT(5)
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#define IRQENB_PENUP BIT(9)
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@@ -277,7 +279,7 @@ static irqreturn_t tscadc_irq(int irq, void *dev)
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unsigned int fsm;
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status = tscadc_readl(ts_dev, REG_IRQSTATUS);
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- if (status & IRQENB_FIFO1THRES) {
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+ if (status & IRQENB_FIFO0THRES) {
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tscadc_read_coordinates(ts_dev, &x, &y);
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z1 = tscadc_readl(ts_dev, REG_FIFO0) & 0xfff;
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@@ -303,7 +305,7 @@ static irqreturn_t tscadc_irq(int irq, void *dev)
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input_sync(input_dev);
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}
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}
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- irqclr |= IRQENB_FIFO1THRES;
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+ irqclr |= IRQENB_FIFO0THRES;
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}
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/*
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@@ -446,9 +448,9 @@ static int __devinit tscadc_probe(struct platform_device *pdev)
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tscadc_writel(ts_dev, REG_CTRL, ctrl);
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tscadc_idle_config(ts_dev);
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- tscadc_writel(ts_dev, REG_IRQENABLE, IRQENB_FIFO1THRES);
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+ tscadc_writel(ts_dev, REG_IRQENABLE, IRQENB_FIFO0THRES);
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tscadc_step_config(ts_dev);
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- tscadc_writel(ts_dev, REG_FIFO1THR, ts_dev->steps_to_configure);
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+ tscadc_writel(ts_dev, REG_FIFO0THR, ts_dev->steps_to_configure);
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ctrl |= CNTRLREG_TSCSSENB;
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tscadc_writel(ts_dev, REG_CTRL, ctrl);
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