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@@ -203,19 +203,23 @@ static int iwl_pcie_apm_init(struct iwl_trans *trans)
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/*
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* Enable DMA clock and wait for it to stabilize.
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*
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- * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
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- * do not disable clocks. This preserves any hardware bits already
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- * set by default in "CLK_CTRL_REG" after reset.
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+ * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
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+ * bits do not disable clocks. This preserves any hardware
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+ * bits already set by default in "CLK_CTRL_REG" after reset.
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*/
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- iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
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- udelay(20);
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+ if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) {
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+ iwl_write_prph(trans, APMG_CLK_EN_REG,
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+ APMG_CLK_VAL_DMA_CLK_RQT);
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+ udelay(20);
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- /* Disable L1-Active */
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- iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
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- APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
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+ /* Disable L1-Active */
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+ iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
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+ APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
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- /* Clear the interrupt in APMG if the NIC is in RFKILL */
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- iwl_write_prph(trans, APMG_RTC_INT_STT_REG, APMG_RTC_INT_STT_RFKILL);
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+ /* Clear the interrupt in APMG if the NIC is in RFKILL */
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+ iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
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+ APMG_RTC_INT_STT_RFKILL);
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+ }
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set_bit(STATUS_DEVICE_ENABLED, &trans->status);
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@@ -273,7 +277,8 @@ static int iwl_pcie_nic_init(struct iwl_trans *trans)
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spin_unlock(&trans_pcie->irq_lock);
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- iwl_pcie_set_pwr(trans, false);
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+ if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
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+ iwl_pcie_set_pwr(trans, false);
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iwl_op_mode_nic_config(trans->op_mode);
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