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@@ -192,6 +192,45 @@ int cudbg_collect_cim_ma_la(struct cudbg_init *pdbg_init,
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return rc;
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}
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+int cudbg_collect_cim_qcfg(struct cudbg_init *pdbg_init,
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+ struct cudbg_buffer *dbg_buff,
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+ struct cudbg_error *cudbg_err)
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+{
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+ struct adapter *padap = pdbg_init->adap;
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+ struct cudbg_buffer temp_buff = { 0 };
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+ struct cudbg_cim_qcfg *cim_qcfg_data;
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+ int rc;
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+
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+ rc = cudbg_get_buff(dbg_buff, sizeof(struct cudbg_cim_qcfg),
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+ &temp_buff);
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+ if (rc)
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+ return rc;
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+
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+ cim_qcfg_data = (struct cudbg_cim_qcfg *)temp_buff.data;
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+ cim_qcfg_data->chip = padap->params.chip;
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+ rc = t4_cim_read(padap, UP_IBQ_0_RDADDR_A,
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+ ARRAY_SIZE(cim_qcfg_data->stat), cim_qcfg_data->stat);
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+ if (rc) {
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+ cudbg_err->sys_err = rc;
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+ cudbg_put_buff(&temp_buff, dbg_buff);
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+ return rc;
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+ }
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+
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+ rc = t4_cim_read(padap, UP_OBQ_0_REALADDR_A,
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+ ARRAY_SIZE(cim_qcfg_data->obq_wr),
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+ cim_qcfg_data->obq_wr);
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+ if (rc) {
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+ cudbg_err->sys_err = rc;
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+ cudbg_put_buff(&temp_buff, dbg_buff);
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+ return rc;
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+ }
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+
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+ t4_read_cimq_cfg(padap, cim_qcfg_data->base, cim_qcfg_data->size,
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+ cim_qcfg_data->thres);
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+ cudbg_write_and_release_buff(&temp_buff, dbg_buff);
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+ return rc;
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+}
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+
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static int cudbg_read_cim_ibq(struct cudbg_init *pdbg_init,
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struct cudbg_buffer *dbg_buff,
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struct cudbg_error *cudbg_err, int qid)
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