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@@ -162,6 +162,21 @@ static const u32 mt6351_regs[] = {
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[PWRAP_DEW_RDDMY_NO] = 0x030C,
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};
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+static const u32 mt6357_regs[] = {
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+ [PWRAP_DEW_DIO_EN] = 0x040A,
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+ [PWRAP_DEW_READ_TEST] = 0x040C,
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+ [PWRAP_DEW_WRITE_TEST] = 0x040E,
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+ [PWRAP_DEW_CRC_EN] = 0x0412,
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+ [PWRAP_DEW_CRC_VAL] = 0x0414,
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+ [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0418,
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+ [PWRAP_DEW_CIPHER_IV_SEL] = 0x041A,
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+ [PWRAP_DEW_CIPHER_EN] = 0x041C,
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+ [PWRAP_DEW_CIPHER_RDY] = 0x041E,
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+ [PWRAP_DEW_CIPHER_MODE] = 0x0420,
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+ [PWRAP_DEW_CIPHER_SWRST] = 0x0422,
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+ [PWRAP_DEW_RDDMY_NO] = 0x0424,
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+};
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+
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static const u32 mt6358_regs[] = {
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[PWRAP_SMT_CON1] = 0x0030,
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[PWRAP_DRV_CON1] = 0x0038,
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@@ -840,6 +855,7 @@ static int mt8183_regs[] = {
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enum pmic_type {
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PMIC_MT6323,
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PMIC_MT6351,
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+ PMIC_MT6357,
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PMIC_MT6358,
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PMIC_MT6380,
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PMIC_MT6397,
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@@ -1305,6 +1321,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
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break;
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case PMIC_MT6323:
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case PMIC_MT6351:
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+ case PMIC_MT6357:
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pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_EN],
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0x1);
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break;
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@@ -1592,6 +1609,15 @@ static const struct pwrap_slv_type pmic_mt6351 = {
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.pwrap_write = pwrap_write16,
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};
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+static const struct pwrap_slv_type pmic_mt6357 = {
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+ .dew_regs = mt6357_regs,
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+ .type = PMIC_MT6357,
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+ .regmap = &pwrap_regmap_config16,
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+ .caps = 0,
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+ .pwrap_read = pwrap_read16,
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+ .pwrap_write = pwrap_write16,
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+};
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+
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static const struct pwrap_slv_type pmic_mt6358 = {
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.dew_regs = mt6358_regs,
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.type = PMIC_MT6358,
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@@ -1627,6 +1653,9 @@ static const struct of_device_id of_slave_match_tbl[] = {
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}, {
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.compatible = "mediatek,mt6351",
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.data = &pmic_mt6351,
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+ }, {
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+ .compatible = "mediatek,mt6357",
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+ .data = &pmic_mt6357,
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}, {
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.compatible = "mediatek,mt6358",
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.data = &pmic_mt6358,
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