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sh: Tidy up some of the cpu legacy dma header mess.

This has turned in to quite a mess, and with CPUs that care using
dmaengine now it's about time to start cleaning up after the legacy DMA
code. For starters, kill off the stubs for the CPUs that don't do
anything, as well as all of the unused definitions. This leaves us with a
set of IRQs and base addresses we can deal with later.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Paul Mundt 13 жил өмнө
parent
commit
2ff9f317f1

+ 0 - 1
arch/sh/include/asm/dma.h

@@ -15,7 +15,6 @@
 #include <linux/wait.h>
 #include <linux/wait.h>
 #include <linux/sched.h>
 #include <linux/sched.h>
 #include <linux/device.h>
 #include <linux/device.h>
-#include <cpu/dma.h>
 #include <asm-generic/dma.h>
 #include <asm-generic/dma.h>
 
 
 #ifdef CONFIG_NR_DMA_CHANNELS
 #ifdef CONFIG_NR_DMA_CHANNELS

+ 0 - 23
arch/sh/include/cpu-sh2/cpu/dma.h

@@ -1,23 +0,0 @@
-/*
- * Definitions for the SH-2 DMAC.
- *
- * Copyright (C) 2003  Paul Mundt
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#ifndef __ASM_CPU_SH2_DMA_H
-#define __ASM_CPU_SH2_DMA_H
-
-#define SH_MAX_DMA_CHANNELS	2
-
-#define SAR	((unsigned long[]){ 0xffffff80, 0xffffff90 })
-#define DAR	((unsigned long[]){ 0xffffff84, 0xffffff94 })
-#define DMATCR	((unsigned long[]){ 0xffffff88, 0xffffff98 })
-#define CHCR	((unsigned long[]){ 0xfffffffc, 0xffffff9c })
-
-#define DMAOR	0xffffffb0
-
-#endif /* __ASM_CPU_SH2_DMA_H */
-

+ 0 - 1
arch/sh/include/cpu-sh2a/cpu/dma.h

@@ -1 +0,0 @@
-#include <cpu-sh2/cpu/dma.h>

+ 0 - 7
arch/sh/include/cpu-sh3/cpu/dma.h

@@ -15,11 +15,4 @@
 #define DMTE0_IRQ	evt2irq(0x800)
 #define DMTE0_IRQ	evt2irq(0x800)
 #define DMTE4_IRQ	evt2irq(0xb80)
 #define DMTE4_IRQ	evt2irq(0xb80)
 
 
-/* Definitions for the SuperH DMAC */
-#define TM_BURST	0x00000020
-#define TS_8		0x00000000
-#define TS_16		0x00000008
-#define TS_32		0x00000010
-#define TS_128		0x00000018
-
 #endif /* __ASM_CPU_SH3_DMA_H */
 #endif /* __ASM_CPU_SH3_DMA_H */

+ 0 - 9
arch/sh/include/cpu-sh4/cpu/dma.h

@@ -14,13 +14,4 @@
 #define SH_DMAC_BASE0	0xffa00000
 #define SH_DMAC_BASE0	0xffa00000
 #define SH_DMAC_BASE1	0xffa00070
 #define SH_DMAC_BASE1	0xffa00070
 
 
-/* Definitions for the SuperH DMAC */
-#define TM_BURST	0x00000080
-#define TS_8		0x00000010
-#define TS_16		0x00000020
-#define TS_32		0x00000030
-#define TS_64		0x00000000
-
-#define DMAOR_COD	0x00000008
-
 #endif /* __ASM_CPU_SH4_DMA_H */
 #endif /* __ASM_CPU_SH4_DMA_H */

+ 0 - 5
arch/sh/include/cpu-sh4a/cpu/dma.h

@@ -77,9 +77,4 @@
 #define SH_DMARS_BASE0	0xFC809000
 #define SH_DMARS_BASE0	0xFC809000
 #endif
 #endif
 
 
-#define REQ_HE		0x000000C0
-#define REQ_H		0x00000080
-#define REQ_LE		0x00000040
-#define TM_BURST	0x00000020
-
 #endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */
 #endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */

+ 0 - 6
arch/sh/include/cpu-sh5/cpu/dma.h

@@ -1,6 +0,0 @@
-#ifndef __ASM_SH_CPU_SH5_DMA_H
-#define __ASM_SH_CPU_SH5_DMA_H
-
-/* Nothing yet */
-
-#endif /* __ASM_SH_CPU_SH5_DMA_H */