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@@ -248,6 +248,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
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int tries;
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u32 training_pattern;
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uint8_t link_status[DP_LINK_STATUS_SIZE];
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+ bool channel_eq = false;
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training_pattern = intel_dp_training_pattern(intel_dp);
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@@ -259,7 +260,6 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
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return false;
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}
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- intel_dp->channel_eq_status = false;
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for (tries = 0; tries < 5; tries++) {
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drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
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@@ -279,7 +279,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
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if (drm_dp_channel_eq_ok(link_status,
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intel_dp->lane_count)) {
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- intel_dp->channel_eq_status = true;
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+ channel_eq = true;
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DRM_DEBUG_KMS("Channel EQ done. DP Training "
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"successful\n");
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break;
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@@ -301,7 +301,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
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intel_dp_set_idle_link_train(intel_dp);
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- return intel_dp->channel_eq_status;
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+ return channel_eq;
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}
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