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@@ -36,6 +36,27 @@
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#include <linux/dmaengine.h>
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#include <linux/dmaengine.h>
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#include <linux/smc91x.h>
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#include <linux/smc91x.h>
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+/*
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+ * Any 16-bit access is performed with two 8-bit accesses if the hardware
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+ * can't do it directly. Most registers are 16-bit so those are mandatory.
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+ */
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+#define SMC_outw_b(x, a, r) \
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+ do { \
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+ unsigned int __val16 = (x); \
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+ unsigned int __reg = (r); \
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+ SMC_outb(__val16, a, __reg); \
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+ SMC_outb(__val16 >> 8, a, __reg + (1 << SMC_IO_SHIFT)); \
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+ } while (0)
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+
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+#define SMC_inw_b(a, r) \
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+ ({ \
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+ unsigned int __val16; \
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+ unsigned int __reg = r; \
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+ __val16 = SMC_inb(a, __reg); \
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+ __val16 |= SMC_inb(a, __reg + (1 << SMC_IO_SHIFT)) << 8; \
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+ __val16; \
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+ })
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+
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/*
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/*
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* Define your architecture specific bus configuration parameters here.
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* Define your architecture specific bus configuration parameters here.
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*/
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*/
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@@ -55,10 +76,30 @@
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#define SMC_IO_SHIFT (lp->io_shift)
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#define SMC_IO_SHIFT (lp->io_shift)
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#define SMC_inb(a, r) readb((a) + (r))
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#define SMC_inb(a, r) readb((a) + (r))
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-#define SMC_inw(a, r) readw((a) + (r))
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+#define SMC_inw(a, r) \
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+ ({ \
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+ unsigned int __smc_r = r; \
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+ SMC_16BIT(lp) ? readw((a) + __smc_r) : \
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+ SMC_8BIT(lp) ? SMC_inw_b(a, __smc_r) : \
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+ ({ BUG(); 0; }); \
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+ })
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+
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#define SMC_inl(a, r) readl((a) + (r))
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#define SMC_inl(a, r) readl((a) + (r))
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#define SMC_outb(v, a, r) writeb(v, (a) + (r))
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#define SMC_outb(v, a, r) writeb(v, (a) + (r))
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+#define SMC_outw(v, a, r) \
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+ do { \
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+ unsigned int __v = v, __smc_r = r; \
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+ if (SMC_16BIT(lp)) \
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+ __SMC_outw(__v, a, __smc_r); \
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+ else if (SMC_8BIT(lp)) \
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+ SMC_outw_b(__v, a, __smc_r); \
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+ else \
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+ BUG(); \
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+ } while (0)
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+
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#define SMC_outl(v, a, r) writel(v, (a) + (r))
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#define SMC_outl(v, a, r) writel(v, (a) + (r))
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+#define SMC_insb(a, r, p, l) readsb((a) + (r), p, l)
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+#define SMC_outsb(a, r, p, l) writesb((a) + (r), p, l)
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#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
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#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
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#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
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#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
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#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
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#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
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@@ -66,7 +107,7 @@
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#define SMC_IRQ_FLAGS (-1) /* from resource */
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#define SMC_IRQ_FLAGS (-1) /* from resource */
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/* We actually can't write halfwords properly if not word aligned */
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/* We actually can't write halfwords properly if not word aligned */
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-static inline void SMC_outw(u16 val, void __iomem *ioaddr, int reg)
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+static inline void __SMC_outw(u16 val, void __iomem *ioaddr, int reg)
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{
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{
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if ((machine_is_mainstone() || machine_is_stargate2() ||
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if ((machine_is_mainstone() || machine_is_stargate2() ||
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machine_is_pxa_idp()) && reg & 2) {
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machine_is_pxa_idp()) && reg & 2) {
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@@ -416,24 +457,8 @@ smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
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#if ! SMC_CAN_USE_16BIT
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#if ! SMC_CAN_USE_16BIT
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-/*
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- * Any 16-bit access is performed with two 8-bit accesses if the hardware
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- * can't do it directly. Most registers are 16-bit so those are mandatory.
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- */
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-#define SMC_outw(x, ioaddr, reg) \
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- do { \
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- unsigned int __val16 = (x); \
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- SMC_outb( __val16, ioaddr, reg ); \
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- SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
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- } while (0)
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-#define SMC_inw(ioaddr, reg) \
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- ({ \
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- unsigned int __val16; \
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- __val16 = SMC_inb( ioaddr, reg ); \
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- __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
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- __val16; \
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- })
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-
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+#define SMC_outw(x, ioaddr, reg) SMC_outw_b(x, ioaddr, reg)
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+#define SMC_inw(ioaddr, reg) SMC_inw_b(ioaddr, reg)
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#define SMC_insw(a, r, p, l) BUG()
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#define SMC_insw(a, r, p, l) BUG()
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#define SMC_outsw(a, r, p, l) BUG()
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#define SMC_outsw(a, r, p, l) BUG()
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