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@@ -193,7 +193,7 @@
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*
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* Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
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*/
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-#define FLEXCAN_QUIRK_BROKEN_ERR_STATE BIT(1) /* [TR]WRN_INT not connected */
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+#define FLEXCAN_QUIRK_BROKEN_WERR_STATE BIT(1) /* [TR]WRN_INT not connected */
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#define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2) /* Disable RX FIFO Global mask */
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#define FLEXCAN_QUIRK_ENABLE_EACEN_RRS BIT(3) /* Enable EACEN and RRS bit in ctrl2 */
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#define FLEXCAN_QUIRK_DISABLE_MECR BIT(4) /* Disable Memory error detection */
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@@ -281,7 +281,7 @@ struct flexcan_priv {
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};
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static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
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- .quirks = FLEXCAN_QUIRK_BROKEN_ERR_STATE,
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+ .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE,
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};
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static const struct flexcan_devtype_data fsl_imx28_devtype_data;
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@@ -767,7 +767,7 @@ static irqreturn_t flexcan_irq(int irq, void *dev_id)
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/* state change interrupt or broken error state quirk fix is enabled */
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if ((reg_esr & FLEXCAN_ESR_ERR_STATE) ||
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- (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_ERR_STATE))
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+ (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE))
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flexcan_irq_state(dev, reg_esr);
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/* bus error IRQ - handle if bus error reporting is activated */
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@@ -888,7 +888,7 @@ static int flexcan_chip_start(struct net_device *dev)
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* on most Flexcan cores, too. Otherwise we don't get
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* any error warning or passive interrupts.
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*/
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- if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_ERR_STATE ||
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+ if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||
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priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
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reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
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else
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