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@@ -75,10 +75,28 @@ gp100_mc_intr_mask(struct nvkm_mc *base, u32 mask, u32 intr)
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spin_unlock_irqrestore(&mc->lock, flags);
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}
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+const struct nvkm_mc_map
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+gp100_mc_intr[] = {
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+ { 0x04000000, NVKM_ENGINE_DISP },
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+ { 0x00000100, NVKM_ENGINE_FIFO },
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+ { 0x00000200, NVKM_SUBDEV_FAULT },
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+ { 0x40000000, NVKM_SUBDEV_IBUS },
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+ { 0x10000000, NVKM_SUBDEV_BUS },
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+ { 0x08000000, NVKM_SUBDEV_FB },
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+ { 0x02000000, NVKM_SUBDEV_LTC },
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+ { 0x01000000, NVKM_SUBDEV_PMU },
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+ { 0x00200000, NVKM_SUBDEV_GPIO },
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+ { 0x00200000, NVKM_SUBDEV_I2C },
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+ { 0x00100000, NVKM_SUBDEV_TIMER },
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+ { 0x00040000, NVKM_SUBDEV_THERM },
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+ { 0x00002000, NVKM_SUBDEV_FB },
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+ {},
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+};
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+
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static const struct nvkm_mc_func
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gp100_mc = {
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.init = nv50_mc_init,
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- .intr = gk104_mc_intr,
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+ .intr = gp100_mc_intr,
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.intr_unarm = gp100_mc_intr_unarm,
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.intr_rearm = gp100_mc_intr_rearm,
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.intr_mask = gp100_mc_intr_mask,
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