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@@ -8717,6 +8717,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
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fourcc = i9xx_format_to_fourcc(pixel_format);
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fb->pixel_format = fourcc;
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fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
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+ fb->format = drm_format_info(fourcc);
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if (INTEL_GEN(dev_priv) >= 4) {
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if (plane_config->tiling)
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@@ -9748,6 +9749,7 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
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val & PLANE_CTL_ALPHA_MASK);
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fb->pixel_format = fourcc;
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fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
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+ fb->format = drm_format_info(fourcc);
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tiling = val & PLANE_CTL_TILED_MASK;
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switch (tiling) {
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@@ -9863,6 +9865,7 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc,
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fourcc = i9xx_format_to_fourcc(pixel_format);
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fb->pixel_format = fourcc;
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fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
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+ fb->format = drm_format_info(fourcc);
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base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
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if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
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