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@@ -296,23 +296,13 @@ qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase,
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return buf;
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}
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-int
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+void
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qla24xx_pause_risc(struct device_reg_24xx __iomem *reg)
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{
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- int rval = QLA_SUCCESS;
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- uint32_t cnt;
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-
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WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE);
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- for (cnt = 30000;
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- ((RD_REG_DWORD(®->host_status) & HSRX_RISC_PAUSED) == 0) &&
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- rval == QLA_SUCCESS; cnt--) {
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- if (cnt)
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- udelay(100);
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- else
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- rval = QLA_FUNCTION_TIMEOUT;
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- }
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- return rval;
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+ /* 100 usec delay is sufficient enough for hardware to pause RISC */
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+ udelay(100);
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}
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int
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@@ -320,10 +310,14 @@ qla24xx_soft_reset(struct qla_hw_data *ha)
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{
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int rval = QLA_SUCCESS;
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uint32_t cnt;
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- uint16_t mb0, wd;
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+ uint16_t wd;
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struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
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- /* Reset RISC. */
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+ /*
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+ * Reset RISC. The delay is dependent on system architecture.
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+ * Driver can proceed with the reset sequence after waiting
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+ * for a timeout period.
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+ */
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WRT_REG_DWORD(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
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for (cnt = 0; cnt < 30000; cnt++) {
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if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
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@@ -337,13 +331,6 @@ qla24xx_soft_reset(struct qla_hw_data *ha)
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pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
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udelay(100);
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- /* Wait for firmware to complete NVRAM accesses. */
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- mb0 = (uint32_t) RD_REG_WORD(®->mailbox0);
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- for (cnt = 10000 ; cnt && mb0; cnt--) {
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- udelay(5);
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- mb0 = (uint32_t) RD_REG_WORD(®->mailbox0);
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- barrier();
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- }
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/* Wait for soft-reset to complete. */
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for (cnt = 0; cnt < 30000; cnt++) {
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@@ -356,10 +343,10 @@ qla24xx_soft_reset(struct qla_hw_data *ha)
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WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET);
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RD_REG_DWORD(®->hccr); /* PCI Posting. */
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- for (cnt = 30000; RD_REG_WORD(®->mailbox0) != 0 &&
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+ for (cnt = 10000; RD_REG_WORD(®->mailbox0) != 0 &&
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rval == QLA_SUCCESS; cnt--) {
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if (cnt)
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- udelay(100);
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+ udelay(10);
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else
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rval = QLA_FUNCTION_TIMEOUT;
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}
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@@ -1075,10 +1062,11 @@ qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
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fw->host_status = htonl(RD_REG_DWORD(®->host_status));
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- /* Pause RISC. */
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- rval = qla24xx_pause_risc(reg);
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- if (rval != QLA_SUCCESS)
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- goto qla24xx_fw_dump_failed_0;
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+ /*
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+ * Pause RISC. No need to track timeout, as resetting the chip
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+ * is the right approach incase of pause timeout
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+ */
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+ qla24xx_pause_risc(reg);
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/* Host interface registers. */
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dmp_reg = ®->flash_addr;
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@@ -1325,10 +1313,11 @@ qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
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fw->host_status = htonl(RD_REG_DWORD(®->host_status));
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- /* Pause RISC. */
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- rval = qla24xx_pause_risc(reg);
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- if (rval != QLA_SUCCESS)
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- goto qla25xx_fw_dump_failed_0;
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+ /*
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+ * Pause RISC. No need to track timeout, as resetting the chip
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+ * is the right approach incase of pause timeout
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+ */
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+ qla24xx_pause_risc(reg);
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/* Host/Risc registers. */
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iter_reg = fw->host_risc_reg;
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@@ -1641,10 +1630,11 @@ qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
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fw->host_status = htonl(RD_REG_DWORD(®->host_status));
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- /* Pause RISC. */
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- rval = qla24xx_pause_risc(reg);
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- if (rval != QLA_SUCCESS)
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- goto qla81xx_fw_dump_failed_0;
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+ /*
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+ * Pause RISC. No need to track timeout, as resetting the chip
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+ * is the right approach incase of pause timeout
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+ */
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+ qla24xx_pause_risc(reg);
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/* Host/Risc registers. */
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iter_reg = fw->host_risc_reg;
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@@ -1959,10 +1949,11 @@ qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
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fw->host_status = htonl(RD_REG_DWORD(®->host_status));
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- /* Pause RISC. */
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- rval = qla24xx_pause_risc(reg);
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- if (rval != QLA_SUCCESS)
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- goto qla83xx_fw_dump_failed_0;
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+ /*
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+ * Pause RISC. No need to track timeout, as resetting the chip
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+ * is the right approach incase of pause timeout
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+ */
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+ qla24xx_pause_risc(reg);
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WRT_REG_DWORD(®->iobase_addr, 0x6000);
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dmp_reg = ®->iobase_window;
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