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@@ -39,6 +39,30 @@
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#define _RPAGE_RPN0 0x01000
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#define _RPAGE_RPN1 0x02000
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+/* Max physical address bit as per radix table */
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+#define _RPAGE_PA_MAX 57
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+
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+/*
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+ * Max physical address bit we will use for now.
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+ *
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+ * This is mostly a hardware limitation and for now Power9 has
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+ * a 51 bit limit.
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+ *
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+ * This is different from the number of physical bit required to address
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+ * the last byte of memory. That is defined by MAX_PHYSMEM_BITS.
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+ * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum
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+ * number of sections we can support (SECTIONS_SHIFT).
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+ *
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+ * This is different from Radix page table limitation above and
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+ * should always be less than that. The limit is done such that
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+ * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX
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+ * for hash linux page table specific bits.
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+ *
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+ * In order to be compatible with future hardware generations we keep
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+ * some offsets and limit this for now to 53
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+ */
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+#define _PAGE_PA_MAX 53
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+
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#define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */
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#define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */
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@@ -51,10 +75,11 @@
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*/
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#define _PAGE_NO_CACHE _PAGE_TOLERANT
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/*
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- * We support 57 bit real address in pte. Clear everything above 57, and
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- * every thing below PAGE_SHIFT;
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+ * We support _RPAGE_PA_MAX bit real address in pte. On the linux side
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+ * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX
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+ * and every thing below PAGE_SHIFT;
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*/
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-#define PTE_RPN_MASK (((1UL << 57) - 1) & (PAGE_MASK))
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+#define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK))
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/*
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* set of bits not changed in pmd_modify. Even though we have hash specific bits
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* in here, on radix we expect them to be zero.
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