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@@ -40,6 +40,7 @@
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#define LAYER2 0x01
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#define MAX_RXTS 64
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#define N_EXT_TS 6
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+#define N_PER_OUT 7
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#define PSF_PTPVER 2
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#define PSF_EVNT 0x4000
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#define PSF_RX 0x2000
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@@ -47,7 +48,6 @@
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#define EXT_EVENT 1
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#define CAL_EVENT 7
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#define CAL_TRIGGER 7
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-#define PER_TRIGGER 6
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#define DP83640_N_PINS 12
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#define MII_DP83640_MICR 0x11
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@@ -300,23 +300,23 @@ static u64 phy2txts(struct phy_txts *p)
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}
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static int periodic_output(struct dp83640_clock *clock,
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- struct ptp_clock_request *clkreq, bool on)
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+ struct ptp_clock_request *clkreq, bool on,
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+ int trigger)
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{
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struct dp83640_private *dp83640 = clock->chosen;
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struct phy_device *phydev = dp83640->phydev;
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u32 sec, nsec, pwidth;
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- u16 gpio, ptp_trig, trigger, val;
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+ u16 gpio, ptp_trig, val;
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if (on) {
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- gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT, 0);
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+ gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT,
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+ trigger);
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if (gpio < 1)
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return -EINVAL;
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} else {
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gpio = 0;
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}
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- trigger = PER_TRIGGER;
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-
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ptp_trig = TRIG_WR |
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(trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT |
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(gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT |
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@@ -353,6 +353,11 @@ static int periodic_output(struct dp83640_clock *clock,
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ext_write(0, phydev, PAGE4, PTP_TDR, sec >> 16); /* sec[31:16] */
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ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff); /* ns[15:0] */
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ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16); /* ns[31:16] */
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+ /* Triggers 0 and 1 has programmable pulsewidth2 */
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+ if (trigger < 2) {
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+ ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff);
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+ ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16);
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+ }
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/*enable trigger*/
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val &= ~TRIG_LOAD;
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@@ -491,9 +496,9 @@ static int ptp_dp83640_enable(struct ptp_clock_info *ptp,
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return 0;
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case PTP_CLK_REQ_PEROUT:
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- if (rq->perout.index != 0)
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+ if (rq->perout.index >= N_PER_OUT)
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return -EINVAL;
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- return periodic_output(clock, rq, on);
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+ return periodic_output(clock, rq, on, rq->perout.index);
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default:
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break;
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@@ -505,6 +510,16 @@ static int ptp_dp83640_enable(struct ptp_clock_info *ptp,
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static int ptp_dp83640_verify(struct ptp_clock_info *ptp, unsigned int pin,
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enum ptp_pin_function func, unsigned int chan)
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{
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+ struct dp83640_clock *clock =
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+ container_of(ptp, struct dp83640_clock, caps);
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+
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+ if (clock->caps.pin_config[pin].func == PTP_PF_PHYSYNC &&
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+ !list_empty(&clock->phylist))
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+ return 1;
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+
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+ if (func == PTP_PF_PHYSYNC)
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+ return 1;
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+
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return 0;
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}
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@@ -594,7 +609,11 @@ static void recalibrate(struct dp83640_clock *clock)
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u16 cal_gpio, cfg0, evnt, ptp_trig, trigger, val;
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trigger = CAL_TRIGGER;
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- cal_gpio = gpio_tab[CALIBRATE_GPIO];
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+ cal_gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PHYSYNC, 0);
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+ if (cal_gpio < 1) {
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+ pr_err("PHY calibration pin not avaible - PHY is not calibrated.");
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+ return;
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+ }
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mutex_lock(&clock->extreg_lock);
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@@ -944,7 +963,7 @@ static void dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus)
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clock->caps.max_adj = 1953124;
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clock->caps.n_alarm = 0;
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clock->caps.n_ext_ts = N_EXT_TS;
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- clock->caps.n_per_out = 1;
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+ clock->caps.n_per_out = N_PER_OUT;
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clock->caps.n_pins = DP83640_N_PINS;
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clock->caps.pps = 0;
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clock->caps.adjfreq = ptp_dp83640_adjfreq;
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