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@@ -873,6 +873,8 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
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/* Initialize the ring buffer's read and write pointers */
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WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
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+ WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
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+
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ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
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WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
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lower_32_bits(ring->wptr));
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@@ -1049,6 +1051,8 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
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/* Initialize the ring buffer's read and write pointers */
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WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
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+ WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
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+
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ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
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WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
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lower_32_bits(ring->wptr));
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@@ -1215,6 +1219,10 @@ static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
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+ WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2,
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+ lower_32_bits(ring->wptr) | 0x80000000);
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+
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WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
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}
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