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@@ -545,6 +545,14 @@ static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev)
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{
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u32 cnfg;
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+ /*
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+ * NACK interrupt is generated before the I2C controller generates
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+ * the STOP condition on the bus. So wait for 2 clock periods
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+ * before disabling the controller so that the STOP condition has
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+ * been delivered properly.
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+ */
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+ udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
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+
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cnfg = i2c_readl(i2c_dev, I2C_CNFG);
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if (cnfg & I2C_CNFG_PACKET_MODE_EN)
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i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, I2C_CNFG);
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@@ -706,15 +714,6 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
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if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
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return 0;
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- /*
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- * NACK interrupt is generated before the I2C controller generates
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- * the STOP condition on the bus. So wait for 2 clock periods
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- * before resetting the controller so that the STOP condition has
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- * been delivered properly.
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- */
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- if (i2c_dev->msg_err == I2C_ERR_NO_ACK)
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- udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
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-
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tegra_i2c_init(i2c_dev);
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if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
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if (msg->flags & I2C_M_IGNORE_NAK)
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