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@@ -55,8 +55,8 @@ static cycle_t nps_clksrc_read(struct clocksource *clksrc)
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return (cycle_t)ioread32be(nps_msu_reg_low_addr[cluster]);
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}
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-static void __init nps_setup_clocksource(struct device_node *node,
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- struct clk *clk)
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+static int __init nps_setup_clocksource(struct device_node *node,
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+ struct clk *clk)
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{
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int ret, cluster;
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@@ -68,7 +68,7 @@ static void __init nps_setup_clocksource(struct device_node *node,
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ret = clk_prepare_enable(clk);
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if (ret) {
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pr_err("Couldn't enable parent clock\n");
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- return;
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+ return ret;
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}
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nps_timer_rate = clk_get_rate(clk);
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@@ -79,20 +79,22 @@ static void __init nps_setup_clocksource(struct device_node *node,
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pr_err("Couldn't register clock source.\n");
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clk_disable_unprepare(clk);
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}
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+
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+ return ret;
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}
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-static void __init nps_timer_init(struct device_node *node)
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+static int __init nps_timer_init(struct device_node *node)
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{
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struct clk *clk;
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clk = of_clk_get(node, 0);
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if (IS_ERR(clk)) {
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pr_err("Can't get timer clock.\n");
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- return;
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+ return PTR_ERR(clk);
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}
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- nps_setup_clocksource(node, clk);
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+ return nps_setup_clocksource(node, clk);
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}
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-CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clksrc, "ezchip,nps400-timer",
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- nps_timer_init);
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+CLOCKSOURCE_OF_DECLARE_RET(ezchip_nps400_clksrc, "ezchip,nps400-timer",
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+ nps_timer_init);
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