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@@ -12935,6 +12935,32 @@ int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp)
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return ret;
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}
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+/**
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+ * get_int_mask - get 64 bit int mask
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+ * @dd - the devdata
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+ * @i - the csr (relative to CCE_INT_MASK)
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+ *
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+ * Returns the mask with the urgent interrupt mask
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+ * bit clear for kernel receive contexts.
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+ */
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+static u64 get_int_mask(struct hfi1_devdata *dd, u32 i)
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+{
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+ u64 mask = U64_MAX; /* default to no change */
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+
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+ if (i >= (IS_RCVURGENT_START / 64) && i < (IS_RCVURGENT_END / 64)) {
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+ int j = (i - (IS_RCVURGENT_START / 64)) * 64;
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+ int k = !j ? IS_RCVURGENT_START % 64 : 0;
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+
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+ if (j)
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+ j -= IS_RCVURGENT_START % 64;
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+ /* j = 0..dd->first_dyn_alloc_ctxt - 1,k = 0..63 */
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+ for (; j < dd->first_dyn_alloc_ctxt && k < 64; j++, k++)
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+ /* convert to bit in mask and clear */
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+ mask &= ~BIT_ULL(k);
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+ }
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+ return mask;
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+}
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+
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/* ========================================================================= */
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/*
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@@ -12948,9 +12974,12 @@ void set_intr_state(struct hfi1_devdata *dd, u32 enable)
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* In HFI, the mask needs to be 1 to allow interrupts.
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*/
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if (enable) {
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- /* enable all interrupts */
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- for (i = 0; i < CCE_NUM_INT_CSRS; i++)
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- write_csr(dd, CCE_INT_MASK + (8 * i), ~(u64)0);
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+ /* enable all interrupts but urgent on kernel contexts */
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+ for (i = 0; i < CCE_NUM_INT_CSRS; i++) {
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+ u64 mask = get_int_mask(dd, i);
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+
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+ write_csr(dd, CCE_INT_MASK + (8 * i), mask);
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+ }
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init_qsfp_int(dd);
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} else {
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