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@@ -1230,6 +1230,18 @@ static void si_detect_hw_virtualization(struct amdgpu_device *adev)
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adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
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}
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+static void si_flush_hdp(struct amdgpu_device *adev)
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+{
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+ WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
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+ RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL);
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+}
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+
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+static void si_invalidate_hdp(struct amdgpu_device *adev)
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+{
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+ WREG32(mmHDP_DEBUG0, 1);
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+ RREG32(mmHDP_DEBUG0);
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+}
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+
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static const struct amdgpu_asic_funcs si_asic_funcs =
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{
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.read_disabled_bios = &si_read_disabled_bios,
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@@ -1241,6 +1253,8 @@ static const struct amdgpu_asic_funcs si_asic_funcs =
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.set_uvd_clocks = &si_set_uvd_clocks,
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.set_vce_clocks = NULL,
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.get_config_memsize = &si_get_config_memsize,
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+ .flush_hdp = &si_flush_hdp,
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+ .invalidate_hdp = &si_invalidate_hdp,
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};
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static uint32_t si_get_rev_id(struct amdgpu_device *adev)
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