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@@ -1,4 +1,23 @@
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-* MTD generic binding
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+* NAND chip and NAND controller generic binding
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+
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+NAND controller/NAND chip representation:
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+
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+The NAND controller should be represented with its own DT node, and all
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+NAND chips attached to this controller should be defined as children nodes
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+of the NAND controller. This representation should be enforced even for
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+simple controllers supporting only one chip.
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+
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+Mandatory NAND controller properties:
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+- #address-cells: depends on your controller. Should at least be 1 to
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+ encode the CS line id.
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+- #size-cells: depends on your controller. Put zero unless you need a
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+ mapping between CS lines and dedicated memory regions
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+
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+Optional NAND controller properties
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+- ranges: only needed if you need to define a mapping between CS lines and
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+ memory regions
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+
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+Optional NAND chip properties:
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- nand-ecc-mode : String, operation mode of the NAND ecc mode.
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Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first",
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@@ -19,3 +38,19 @@ errors per {size} bytes".
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The interpretation of these parameters is implementation-defined, so not all
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implementations must support all possible combinations. However, implementations
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are encouraged to further specify the value(s) they support.
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+
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+Example:
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+
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+ nand-controller {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ /* controller specific properties */
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+
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+ nand@0 {
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+ reg = <0>;
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+ nand-ecc-mode = "soft_bch";
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+
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+ /* controller specific properties */
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+ };
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+ };
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