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@@ -51,9 +51,11 @@
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#define SCLK_SDIO_SAMPLE 119
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#define SCLK_SDIO_SAMPLE 119
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#define SCLK_EMMC_SAMPLE 121
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#define SCLK_EMMC_SAMPLE 121
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#define SCLK_VOP 122
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#define SCLK_VOP 122
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+#define SCLK_HDMI_HDCP 123
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/* dclk gates */
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/* dclk gates */
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#define DCLK_VOP 190
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#define DCLK_VOP 190
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+#define DCLK_HDMI_PHY 191
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/* aclk gates */
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/* aclk gates */
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#define ACLK_DMAC 194
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#define ACLK_DMAC 194
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@@ -78,6 +80,8 @@
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#define PCLK_PWM 350
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#define PCLK_PWM 350
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#define PCLK_TIMER 353
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#define PCLK_TIMER 353
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#define PCLK_PERI 363
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#define PCLK_PERI 363
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+#define PCLK_HDMI_CTRL 364
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+#define PCLK_HDMI_PHY 365
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/* hclk gates */
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/* hclk gates */
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#define HCLK_VOP 452
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#define HCLK_VOP 452
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