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@@ -504,9 +504,13 @@
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#define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1)
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/* RX FIFO constants */
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-#define MVPP2_RX_FIFO_PORT_DATA_SIZE 0x2000
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-#define MVPP2_RX_FIFO_PORT_ATTR_SIZE 0x80
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-#define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80
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+#define MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB 0x8000
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+#define MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB 0x2000
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+#define MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB 0x1000
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+#define MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB 0x200
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+#define MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB 0x80
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+#define MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB 0x40
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+#define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80
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/* RX buffer constants */
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#define MVPP2_SKB_SHINFO_SIZE \
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@@ -7764,9 +7768,42 @@ static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
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for (port = 0; port < MVPP2_MAX_PORTS; port++) {
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mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
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- MVPP2_RX_FIFO_PORT_DATA_SIZE);
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+ MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB);
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mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
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- MVPP2_RX_FIFO_PORT_ATTR_SIZE);
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+ MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB);
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+ }
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+
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+ mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
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+ MVPP2_RX_FIFO_PORT_MIN_PKT);
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+ mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
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+}
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+
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+static void mvpp22_rx_fifo_init(struct mvpp2 *priv)
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+{
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+ int port;
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+
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+ /* The FIFO size parameters are set depending on the maximum speed a
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+ * given port can handle:
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+ * - Port 0: 10Gbps
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+ * - Port 1: 2.5Gbps
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+ * - Ports 2 and 3: 1Gbps
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+ */
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+
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+ mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(0),
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+ MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB);
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+ mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(0),
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+ MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB);
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+
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+ mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(1),
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+ MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB);
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+ mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(1),
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+ MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB);
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+
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+ for (port = 2; port < MVPP2_MAX_PORTS; port++) {
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+ mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
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+ MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB);
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+ mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
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+ MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB);
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}
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mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
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@@ -7870,7 +7907,10 @@ static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv)
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}
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/* Rx Fifo Init */
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- mvpp2_rx_fifo_init(priv);
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+ if (priv->hw_version == MVPP21)
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+ mvpp2_rx_fifo_init(priv);
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+ else
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+ mvpp22_rx_fifo_init(priv);
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if (priv->hw_version == MVPP21)
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writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
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