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@@ -41,6 +41,8 @@ struct ti_qspi_regs {
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};
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struct ti_qspi {
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+ struct completion transfer_complete;
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+
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/* list synchronization */
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struct mutex list_lock;
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@@ -54,6 +56,9 @@ struct ti_qspi {
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struct ti_qspi_regs ctx_reg;
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+ dma_addr_t mmap_phys_base;
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+ struct dma_chan *rx_chan;
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+
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u32 spi_max_frequency;
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u32 cmd;
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u32 dc;
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@@ -379,6 +384,72 @@ static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t,
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return 0;
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}
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+static void ti_qspi_dma_callback(void *param)
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+{
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+ struct ti_qspi *qspi = param;
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+
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+ complete(&qspi->transfer_complete);
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+}
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+
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+static int ti_qspi_dma_xfer(struct ti_qspi *qspi, dma_addr_t dma_dst,
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+ dma_addr_t dma_src, size_t len)
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+{
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+ struct dma_chan *chan = qspi->rx_chan;
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+ struct dma_device *dma_dev = chan->device;
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+ dma_cookie_t cookie;
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+ enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
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+ struct dma_async_tx_descriptor *tx;
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+ int ret;
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+
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+ tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
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+ len, flags);
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+ if (!tx) {
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+ dev_err(qspi->dev, "device_prep_dma_memcpy error\n");
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+ return -EIO;
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+ }
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+
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+ tx->callback = ti_qspi_dma_callback;
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+ tx->callback_param = qspi;
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+ cookie = tx->tx_submit(tx);
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+
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+ ret = dma_submit_error(cookie);
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+ if (ret) {
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+ dev_err(qspi->dev, "dma_submit_error %d\n", cookie);
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+ return -EIO;
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+ }
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+
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+ dma_async_issue_pending(chan);
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+ ret = wait_for_completion_timeout(&qspi->transfer_complete,
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+ msecs_to_jiffies(len));
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+ if (ret <= 0) {
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+ dmaengine_terminate_sync(chan);
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+ dev_err(qspi->dev, "DMA wait_for_completion_timeout\n");
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+ return -ETIMEDOUT;
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+ }
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+
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+ return 0;
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+}
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+
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+static int ti_qspi_dma_xfer_sg(struct ti_qspi *qspi, struct sg_table rx_sg,
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+ loff_t from)
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+{
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+ struct scatterlist *sg;
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+ dma_addr_t dma_src = qspi->mmap_phys_base + from;
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+ dma_addr_t dma_dst;
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+ int i, len, ret;
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+
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+ for_each_sg(rx_sg.sgl, sg, rx_sg.nents, i) {
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+ dma_dst = sg_dma_address(sg);
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+ len = sg_dma_len(sg);
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+ ret = ti_qspi_dma_xfer(qspi, dma_dst, dma_src, len);
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+ if (ret)
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+ return ret;
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+ dma_src += len;
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+ }
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+
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+ return 0;
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+}
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+
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static void ti_qspi_enable_memory_map(struct spi_device *spi)
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{
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struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
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@@ -426,7 +497,7 @@ static void ti_qspi_setup_mmap_read(struct spi_device *spi,
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QSPI_SPI_SETUP_REG(spi->chip_select));
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}
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-static int ti_qspi_spi_flash_read(struct spi_device *spi,
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+static int ti_qspi_spi_flash_read(struct spi_device *spi,
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struct spi_flash_read_message *msg)
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{
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struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
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@@ -437,9 +508,23 @@ static int ti_qspi_spi_flash_read(struct spi_device *spi,
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if (!qspi->mmap_enabled)
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ti_qspi_enable_memory_map(spi);
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ti_qspi_setup_mmap_read(spi, msg);
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- memcpy_fromio(msg->buf, qspi->mmap_base + msg->from, msg->len);
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+
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+ if (qspi->rx_chan) {
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+ if (msg->cur_msg_mapped) {
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+ ret = ti_qspi_dma_xfer_sg(qspi, msg->rx_sg, msg->from);
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+ if (ret)
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+ goto err_unlock;
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+ } else {
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+ dev_err(qspi->dev, "Invalid address for DMA\n");
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+ ret = -EIO;
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+ goto err_unlock;
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+ }
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+ } else {
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+ memcpy_fromio(msg->buf, qspi->mmap_base + msg->from, msg->len);
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+ }
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msg->retlen = msg->len;
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+err_unlock:
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mutex_unlock(&qspi->list_lock);
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return ret;
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@@ -536,6 +621,7 @@ static int ti_qspi_probe(struct platform_device *pdev)
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struct device_node *np = pdev->dev.of_node;
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u32 max_freq;
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int ret = 0, num_cs, irq;
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+ dma_cap_mask_t mask;
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master = spi_alloc_master(&pdev->dev, sizeof(*qspi));
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if (!master)
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@@ -550,6 +636,7 @@ static int ti_qspi_probe(struct platform_device *pdev)
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master->dev.of_node = pdev->dev.of_node;
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master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
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SPI_BPW_MASK(8);
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+ master->spi_flash_read = ti_qspi_spi_flash_read;
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if (!of_property_read_u32(np, "num-cs", &num_cs))
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master->num_chipselect = num_cs;
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@@ -592,17 +679,6 @@ static int ti_qspi_probe(struct platform_device *pdev)
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goto free_master;
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}
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- if (res_mmap) {
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- qspi->mmap_base = devm_ioremap_resource(&pdev->dev,
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- res_mmap);
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- master->spi_flash_read = ti_qspi_spi_flash_read;
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- if (IS_ERR(qspi->mmap_base)) {
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- dev_err(&pdev->dev,
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- "falling back to PIO mode\n");
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- master->spi_flash_read = NULL;
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- }
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- }
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- qspi->mmap_enabled = false;
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if (of_property_read_bool(np, "syscon-chipselects")) {
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qspi->ctrl_base =
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@@ -633,11 +709,37 @@ static int ti_qspi_probe(struct platform_device *pdev)
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if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
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qspi->spi_max_frequency = max_freq;
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- ret = devm_spi_register_master(&pdev->dev, master);
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- if (ret)
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- goto free_master;
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+ dma_cap_zero(mask);
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+ dma_cap_set(DMA_MEMCPY, mask);
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- return 0;
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+ qspi->rx_chan = dma_request_chan_by_mask(&mask);
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+ if (!qspi->rx_chan) {
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+ dev_err(qspi->dev,
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+ "No Rx DMA available, trying mmap mode\n");
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+ ret = 0;
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+ goto no_dma;
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+ }
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+ master->dma_rx = qspi->rx_chan;
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+ init_completion(&qspi->transfer_complete);
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+ if (res_mmap)
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+ qspi->mmap_phys_base = (dma_addr_t)res_mmap->start;
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+
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+no_dma:
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+ if (!qspi->rx_chan && res_mmap) {
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+ qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
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+ if (IS_ERR(qspi->mmap_base)) {
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+ dev_info(&pdev->dev,
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+ "mmap failed with error %ld using PIO mode\n",
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+ PTR_ERR(qspi->mmap_base));
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+ qspi->mmap_base = NULL;
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+ master->spi_flash_read = NULL;
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+ }
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+ }
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+ qspi->mmap_enabled = false;
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+
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+ ret = devm_spi_register_master(&pdev->dev, master);
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+ if (!ret)
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+ return 0;
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free_master:
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spi_master_put(master);
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@@ -656,6 +758,9 @@ static int ti_qspi_remove(struct platform_device *pdev)
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pm_runtime_put_sync(&pdev->dev);
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pm_runtime_disable(&pdev->dev);
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+ if (qspi->rx_chan)
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+ dma_release_channel(qspi->rx_chan);
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+
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return 0;
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}
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