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@@ -109,6 +109,19 @@
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#define MAX_CHNL_GROUP_24G 6
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#define MAX_CHNL_GROUP_5G 14
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+#define TX_PWR_BY_RATE_NUM_BAND 2
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+#define TX_PWR_BY_RATE_NUM_RF 4
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+#define TX_PWR_BY_RATE_NUM_SECTION 12
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+#define MAX_BASE_NUM_IN_PHY_REG_PG_24G 6
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+#define MAX_BASE_NUM_IN_PHY_REG_PG_5G 5
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+
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+enum rf_tx_num {
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+ RF_1TX = 0,
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+ RF_2TX,
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+ RF_MAX_TX_NUM,
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+ RF_TX_NUM_NONIMPLEMENT,
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+};
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+
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struct txpower_info_2g {
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u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
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u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
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@@ -129,6 +142,15 @@ struct txpower_info_5g {
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u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
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};
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+enum rate_section {
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+ CCK = 0,
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+ OFDM,
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+ HT_MCS0_MCS7,
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+ HT_MCS8_MCS15,
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+ VHT_1SSMCS0_1SSMCS9,
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+ VHT_2SSMCS0_2SSMCS9,
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+};
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+
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enum intf_type {
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INTF_PCI = 0,
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INTF_USB = 1,
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@@ -200,6 +222,12 @@ enum hardware_type {
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_pdesc->rxmcs == DESC92_RATE5_5M || \
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_pdesc->rxmcs == DESC92_RATE11M)
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+#define RTL8723E_RX_HAL_IS_CCK_RATE(rxmcs) \
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+ ((rxmcs) == DESC92_RATE1M || \
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+ (rxmcs) == DESC92_RATE2M || \
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+ (rxmcs) == DESC92_RATE5_5M || \
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+ (rxmcs) == DESC92_RATE11M)
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+
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enum scan_operation_backup_opt {
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SCAN_OPT_BACKUP = 0,
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SCAN_OPT_RESTORE,
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@@ -335,6 +363,7 @@ enum hw_variables {
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HAL_DEF_WOWLAN,
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HW_VAR_MRC,
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+ HW_VAR_KEEP_ALIVE,
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HW_VAR_MGT_FILTER,
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HW_VAR_CTRL_FILTER,
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@@ -353,34 +382,34 @@ enum rt_oem_id {
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RT_CID_8187_HW_LED = 3,
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RT_CID_8187_NETGEAR = 4,
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RT_CID_WHQL = 5,
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- RT_CID_819x_CAMEO = 6,
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- RT_CID_819x_RUNTOP = 7,
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- RT_CID_819x_Senao = 8,
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+ RT_CID_819X_CAMEO = 6,
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+ RT_CID_819X_RUNTOP = 7,
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+ RT_CID_819X_SENAO = 8,
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RT_CID_TOSHIBA = 9,
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- RT_CID_819x_Netcore = 10,
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- RT_CID_Nettronix = 11,
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+ RT_CID_819X_NETCORE = 10,
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+ RT_CID_NETTRONIX = 11,
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RT_CID_DLINK = 12,
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RT_CID_PRONET = 13,
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RT_CID_COREGA = 14,
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- RT_CID_819x_ALPHA = 15,
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- RT_CID_819x_Sitecom = 16,
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+ RT_CID_819X_ALPHA = 15,
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+ RT_CID_819X_SITECOM = 16,
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RT_CID_CCX = 17,
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- RT_CID_819x_Lenovo = 18,
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- RT_CID_819x_QMI = 19,
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- RT_CID_819x_Edimax_Belkin = 20,
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- RT_CID_819x_Sercomm_Belkin = 21,
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- RT_CID_819x_CAMEO1 = 22,
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- RT_CID_819x_MSI = 23,
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- RT_CID_819x_Acer = 24,
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- RT_CID_819x_HP = 27,
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- RT_CID_819x_CLEVO = 28,
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- RT_CID_819x_Arcadyan_Belkin = 29,
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- RT_CID_819x_SAMSUNG = 30,
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- RT_CID_819x_WNC_COREGA = 31,
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- RT_CID_819x_Foxcoon = 32,
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- RT_CID_819x_DELL = 33,
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- RT_CID_819x_PRONETS = 34,
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- RT_CID_819x_Edimax_ASUS = 35,
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+ RT_CID_819X_LENOVO = 18,
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+ RT_CID_819X_QMI = 19,
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+ RT_CID_819X_EDIMAX_BELKIN = 20,
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+ RT_CID_819X_SERCOMM_BELKIN = 21,
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+ RT_CID_819X_CAMEO1 = 22,
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+ RT_CID_819X_MSI = 23,
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+ RT_CID_819X_ACER = 24,
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+ RT_CID_819X_HP = 27,
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+ RT_CID_819X_CLEVO = 28,
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+ RT_CID_819X_ARCADYAN_BELKIN = 29,
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+ RT_CID_819X_SAMSUNG = 30,
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+ RT_CID_819X_WNC_COREGA = 31,
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+ RT_CID_819X_FOXCOON = 32,
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+ RT_CID_819X_DELL = 33,
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+ RT_CID_819X_PRONETS = 34,
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+ RT_CID_819X_EDIMAX_ASUS = 35,
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RT_CID_NETGEAR = 36,
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RT_CID_PLANEX = 37,
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RT_CID_CC_C = 38,
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@@ -613,7 +642,7 @@ enum rtl_led_pin {
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enum acm_method {
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eAcmWay0_SwAndHw = 0,
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eAcmWay1_HW = 1,
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- eAcmWay2_SW = 2,
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+ EACMWAY2_SW = 2,
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};
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enum macphy_mode {
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@@ -822,9 +851,9 @@ struct rate_adaptive {
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u32 high_rssi_thresh_for_ra;
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u32 high2low_rssi_thresh_for_ra;
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u8 low2high_rssi_thresh_for_ra40m;
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- u32 low_rssi_thresh_for_ra40M;
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+ u32 low_rssi_thresh_for_ra40m;
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u8 low2high_rssi_thresh_for_ra20m;
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- u32 low_rssi_thresh_for_ra20M;
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+ u32 low_rssi_thresh_for_ra20m;
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u32 upper_rssi_threshold_ratr;
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u32 middleupper_rssi_threshold_ratr;
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u32 middle_rssi_threshold_ratr;
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@@ -991,6 +1020,13 @@ struct rtl_phy {
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u8 cck_high_power;
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/* MAX_PG_GROUP groups of pwr diff by rates */
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u32 mcs_offset[MAX_PG_GROUP][16];
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+ u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND]
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+ [TX_PWR_BY_RATE_NUM_RF]
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+ [TX_PWR_BY_RATE_NUM_RF]
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+ [TX_PWR_BY_RATE_NUM_SECTION];
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+ u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF]
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+ [TX_PWR_BY_RATE_NUM_RF]
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+ [MAX_BASE_NUM_IN_PHY_REG_PG_24G];
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u8 default_initialgain[4];
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/* the current Tx power level */
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@@ -1218,6 +1254,7 @@ struct rtl_hal {
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bool being_init_adapter;
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bool bbrf_ready;
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bool mac_func_enable;
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+ bool pre_edcca_enable;
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struct bt_coexist_8723 hal_coex_8723;
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enum intf_type interface;
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@@ -1326,6 +1363,16 @@ struct fast_ant_training {
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bool becomelinked;
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};
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+struct dm_phy_dbg_info {
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+ char rx_snrdb[4];
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+ u64 num_qry_phy_status;
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+ u64 num_qry_phy_status_cck;
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+ u64 num_qry_phy_status_ofdm;
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+ u16 num_qry_beacon_pkt;
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+ u16 num_non_be_pkt;
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+ s32 rx_evm[4];
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+};
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+
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struct rtl_dm {
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/*PHY status for Dynamic Management */
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long entry_min_undec_sm_pwdb;
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@@ -1367,14 +1414,28 @@ struct rtl_dm {
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bool disable_tx_int;
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char ofdm_index[2];
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char cck_index;
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- char delta_power_index;
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- char delta_power_index_last;
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- char power_index_offset;
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+ char delta_power_index[MAX_RF_PATH];
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+ char delta_power_index_last[MAX_RF_PATH];
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+ char power_index_offset[MAX_RF_PATH];
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+
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+ bool one_entry_only;
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+ struct dm_phy_dbg_info dbginfo;
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+
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+ /* Dynamic ATC switch */
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+ bool atc_status;
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+ bool large_cfo_hit;
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+ bool is_freeze;
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+ int cfo_tail[2];
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+ int cfo_ave_pre;
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+ int crystal_cap;
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+ u8 cfo_threshold;
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+ u32 packet_count;
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+ u32 packet_count_pre;
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/*88e tx power tracking*/
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u8 swing_idx_ofdm[2];
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u8 swing_idx_ofdm_cur;
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- u8 swing_idx_ofdm_base;
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+ u8 swing_idx_ofdm_base[MAX_RF_PATH];
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bool swing_flag_ofdm;
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u8 swing_idx_cck;
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u8 swing_idx_cck_cur;
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@@ -1427,12 +1488,14 @@ struct rtl_efuse {
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u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
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u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
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u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
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- u8 eeprom_chnlarea_txpwr_cck[2][CHANNEL_GROUP_MAX_2G];
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- u8 eeprom_chnlarea_txpwr_ht40_1s[2][CHANNEL_GROUP_MAX];
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- u8 eprom_chnl_txpwr_ht40_2sdf[2][CHANNEL_GROUP_MAX];
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+ u8 eeprom_chnlarea_txpwr_cck[MAX_RF_PATH][CHANNEL_GROUP_MAX_2G];
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+ u8 eeprom_chnlarea_txpwr_ht40_1s[MAX_RF_PATH][CHANNEL_GROUP_MAX];
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+ u8 eprom_chnl_txpwr_ht40_2sdf[MAX_RF_PATH][CHANNEL_GROUP_MAX];
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u8 txpwrlevel_cck[2][CHANNEL_MAX_NUMBER_2G];
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- u8 txpwrlevel_ht40_1s[2][CHANNEL_MAX_NUMBER]; /*For HT 40MHZ pwr */
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- u8 txpwrlevel_ht40_2s[2][CHANNEL_MAX_NUMBER]; /*For HT 40MHZ pwr */
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+ /* For HT 40MHZ pwr */
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+ u8 txpwrlevel_ht40_1s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
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+ u8 txpwrlevel_ht40_2s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
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+ u8 txpwr_ht40diff[MAX_RF_PATH][MAX_TX_COUNT];/*BW40_24G_Diff*/
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u8 internal_pa_5g[2]; /* pathA / pathB */
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u8 eeprom_c9;
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@@ -1705,6 +1768,8 @@ struct rtl_hal_ops {
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enum led_ctl_mode ledaction);
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void (*set_desc) (u8 *pdesc, bool istx, u8 desc_name, u8 *val);
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u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
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+ bool (*is_tx_desc_closed) (struct ieee80211_hw *hw,
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+ u8 hw_queue, u16 index);
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void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue);
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void (*enable_hw_sec) (struct ieee80211_hw *hw);
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void (*set_key) (struct ieee80211_hw *hw, u32 key_index,
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@@ -1743,6 +1808,7 @@ struct rtl_hal_ops {
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void (*bt_coex_off_before_lps) (struct ieee80211_hw *hw);
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void (*fill_h2c_cmd) (struct ieee80211_hw *hw, u8 element_id,
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u32 cmd_len, u8 *p_cmdbuffer);
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+ bool (*get_btc_status) (void);
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};
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struct rtl_intf_ops {
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@@ -1920,6 +1986,7 @@ struct ps_t {
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u8 cur_ccasate;
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u8 pre_rfstate;
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u8 cur_rfstate;
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+ u8 initialize;
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long rssi_val_min;
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};
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@@ -1977,6 +2044,7 @@ struct dig_t {
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char backoffval_range_min;
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u8 dig_min_0;
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u8 dig_min_1;
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+ u8 bt30_cur_igi;
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bool media_connect_0;
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bool media_connect_1;
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@@ -1997,9 +2065,61 @@ struct rtl_btc_info {
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u8 ant_num;
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};
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-struct rtl_bt_coexist {
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+struct bt_coexist_info {
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struct rtl_btc_ops *btc_ops;
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struct rtl_btc_info btc_info;
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+ /* EEPROM BT info. */
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+ u8 eeprom_bt_coexist;
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+ u8 eeprom_bt_type;
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+ u8 eeprom_bt_ant_num;
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+ u8 eeprom_bt_ant_isol;
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+ u8 eeprom_bt_radio_shared;
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+
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+ u8 bt_coexistence;
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+ u8 bt_ant_num;
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+ u8 bt_coexist_type;
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+ u8 bt_state;
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+ u8 bt_cur_state; /* 0:on, 1:off */
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+ u8 bt_ant_isolation; /* 0:good, 1:bad */
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+ u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */
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+ u8 bt_service;
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+ u8 bt_radio_shared_type;
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+ u8 bt_rfreg_origin_1e;
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+ u8 bt_rfreg_origin_1f;
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+ u8 bt_rssi_state;
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+ u32 ratio_tx;
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+ u32 ratio_pri;
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+ u32 bt_edca_ul;
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+ u32 bt_edca_dl;
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+
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+ bool init_set;
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+ bool bt_busy_traffic;
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+ bool bt_traffic_mode_set;
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+ bool bt_non_traffic_mode_set;
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+
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+ bool fw_coexist_all_off;
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+ bool sw_coexist_all_off;
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+ bool hw_coexist_all_off;
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+ u32 cstate;
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+ u32 previous_state;
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+ u32 cstate_h;
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+ u32 previous_state_h;
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+
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+ u8 bt_pre_rssi_state;
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+ u8 bt_pre_rssi_state1;
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+
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+ u8 reg_bt_iso;
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+ u8 reg_bt_sco;
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+ bool balance_on;
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+ u8 bt_active_zero_cnt;
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+ bool cur_bt_disabled;
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+ bool pre_bt_disabled;
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+
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+ u8 bt_profile_case;
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+ u8 bt_profile_action;
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+ bool bt_busy;
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+ bool hold_for_bt_operation;
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+ u8 lps_counter;
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};
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struct rtl_btc_ops {
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@@ -2098,7 +2218,7 @@ struct rtl_priv {
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struct proxim proximity;
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/*for bt coexist use*/
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- struct rtl_bt_coexist btcoexist;
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+ struct bt_coexist_info btcoexist;
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/* separate 92ee from other ICs,
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* 92ee use new trx flow.
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@@ -2164,62 +2284,6 @@ enum bt_radio_shared {
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BT_RADIO_INDIVIDUAL = 1,
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};
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-struct bt_coexist_info {
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-
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- /* EEPROM BT info. */
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- u8 eeprom_bt_coexist;
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- u8 eeprom_bt_type;
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- u8 eeprom_bt_ant_num;
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- u8 eeprom_bt_ant_isol;
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- u8 eeprom_bt_radio_shared;
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-
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- u8 bt_coexistence;
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- u8 bt_ant_num;
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- u8 bt_coexist_type;
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- u8 bt_state;
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- u8 bt_cur_state; /* 0:on, 1:off */
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- u8 bt_ant_isolation; /* 0:good, 1:bad */
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- u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */
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- u8 bt_service;
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- u8 bt_radio_shared_type;
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- u8 bt_rfreg_origin_1e;
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- u8 bt_rfreg_origin_1f;
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- u8 bt_rssi_state;
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- u32 ratio_tx;
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- u32 ratio_pri;
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- u32 bt_edca_ul;
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- u32 bt_edca_dl;
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|
-
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- bool init_set;
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|
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- bool bt_busy_traffic;
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- bool bt_traffic_mode_set;
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|
|
- bool bt_non_traffic_mode_set;
|
|
|
-
|
|
|
- bool fw_coexist_all_off;
|
|
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- bool sw_coexist_all_off;
|
|
|
- bool hw_coexist_all_off;
|
|
|
- u32 cstate;
|
|
|
- u32 previous_state;
|
|
|
- u32 cstate_h;
|
|
|
- u32 previous_state_h;
|
|
|
-
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|
|
- u8 bt_pre_rssi_state;
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|
|
- u8 bt_pre_rssi_state1;
|
|
|
-
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|
|
- u8 reg_bt_iso;
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|
|
- u8 reg_bt_sco;
|
|
|
- bool balance_on;
|
|
|
- u8 bt_active_zero_cnt;
|
|
|
- bool cur_bt_disabled;
|
|
|
- bool pre_bt_disabled;
|
|
|
-
|
|
|
- u8 bt_profile_case;
|
|
|
- u8 bt_profile_action;
|
|
|
- bool bt_busy;
|
|
|
- bool hold_for_bt_operation;
|
|
|
- u8 lps_counter;
|
|
|
-};
|
|
|
-
|
|
|
|
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/****************************************
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|
|
mem access macro define start
|
Larry Finger