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@@ -3073,37 +3073,6 @@ static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
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chv_phy_powergate_lanes(encoder, false, 0x0);
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}
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-/*
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- * Native read with retry for link status and receiver capability reads for
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- * cases where the sink may still be asleep.
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- *
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- * Sinks are *supposed* to come up within 1ms from an off state, but we're also
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- * supposed to retry 3 times per the spec.
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- */
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-static ssize_t
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-intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
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- void *buffer, size_t size)
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-{
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- ssize_t ret;
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- int i;
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-
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- /*
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- * Sometime we just get the same incorrect byte repeated
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- * over the entire buffer. Doing just one throw away read
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- * initially seems to "solve" it.
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- */
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- drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);
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-
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- for (i = 0; i < 3; i++) {
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- ret = drm_dp_dpcd_read(aux, offset, buffer, size);
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- if (ret == size)
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- return ret;
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- msleep(1);
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- }
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-
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- return ret;
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-}
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-
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/*
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* Fetch AUX CH registers 0x202 - 0x207 which contain
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* link status information
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@@ -3111,10 +3080,8 @@ intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
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bool
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intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
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{
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- return intel_dp_dpcd_read_wake(&intel_dp->aux,
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- DP_LANE0_1_STATUS,
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- link_status,
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- DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
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+ return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
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+ DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
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}
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/* These are source-specific values. */
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@@ -3749,8 +3716,8 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint8_t rev;
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- if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
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- sizeof(intel_dp->dpcd)) < 0)
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+ if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
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+ sizeof(intel_dp->dpcd)) < 0)
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return false; /* aux transfer failed */
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DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
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@@ -3758,8 +3725,8 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
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if (intel_dp->dpcd[DP_DPCD_REV] == 0)
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return false; /* DPCD not present */
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- if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
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- &intel_dp->sink_count, 1) < 0)
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+ if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT,
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+ &intel_dp->sink_count, 1) < 0)
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return false;
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/*
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@@ -3782,9 +3749,9 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
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/* Check if the panel supports PSR */
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memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
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if (is_edp(intel_dp)) {
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- intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
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- intel_dp->psr_dpcd,
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- sizeof(intel_dp->psr_dpcd));
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+ drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
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+ intel_dp->psr_dpcd,
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+ sizeof(intel_dp->psr_dpcd));
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if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
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dev_priv->psr.sink_support = true;
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DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
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@@ -3795,9 +3762,9 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
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uint8_t frame_sync_cap;
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dev_priv->psr.sink_support = true;
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- intel_dp_dpcd_read_wake(&intel_dp->aux,
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- DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
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- &frame_sync_cap, 1);
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+ drm_dp_dpcd_read(&intel_dp->aux,
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+ DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
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+ &frame_sync_cap, 1);
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dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
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/* PSR2 needs frame sync as well */
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dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
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@@ -3813,15 +3780,13 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
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/* Intermediate frequency support */
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if (is_edp(intel_dp) &&
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(intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
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- (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
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+ (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
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(rev >= 0x03)) { /* eDp v1.4 or higher */
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__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
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int i;
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- intel_dp_dpcd_read_wake(&intel_dp->aux,
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- DP_SUPPORTED_LINK_RATES,
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- sink_rates,
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- sizeof(sink_rates));
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+ drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
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+ sink_rates, sizeof(sink_rates));
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for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
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int val = le16_to_cpu(sink_rates[i]);
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@@ -3844,9 +3809,9 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
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if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
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return true; /* no per-port downstream info */
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- if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
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- intel_dp->downstream_ports,
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- DP_MAX_DOWNSTREAM_PORTS) < 0)
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+ if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
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+ intel_dp->downstream_ports,
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+ DP_MAX_DOWNSTREAM_PORTS) < 0)
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return false; /* downstream port status fetch failed */
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return true;
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@@ -3860,11 +3825,11 @@ intel_dp_probe_oui(struct intel_dp *intel_dp)
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if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
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return;
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- if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
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+ if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
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DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
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buf[0], buf[1], buf[2]);
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- if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
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+ if (drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
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DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
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buf[0], buf[1], buf[2]);
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}
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@@ -3883,7 +3848,7 @@ intel_dp_probe_mst(struct intel_dp *intel_dp)
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if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
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return false;
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- if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
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+ if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
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if (buf[0] & DP_MST_CAP) {
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DRM_DEBUG_KMS("Sink is MST capable\n");
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intel_dp->is_mst = true;
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@@ -4020,7 +3985,7 @@ stop:
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static bool
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intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
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{
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- return intel_dp_dpcd_read_wake(&intel_dp->aux,
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+ return drm_dp_dpcd_read(&intel_dp->aux,
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DP_DEVICE_SERVICE_IRQ_VECTOR,
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sink_irq_vector, 1) == 1;
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}
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@@ -4030,7 +3995,7 @@ intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
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{
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int ret;
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- ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
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+ ret = drm_dp_dpcd_read(&intel_dp->aux,
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DP_SINK_COUNT_ESI,
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sink_irq_vector, 14);
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if (ret != 14)
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