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@@ -33,12 +33,25 @@
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#define CREATE_TRACE_POINTS
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#include "hda_intel_trace.h"
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+/* DSP lock helpers */
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+#ifdef CONFIG_SND_HDA_DSP_LOADER
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+#define dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex)
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+#define dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex)
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+#define dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex)
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+#define dsp_is_locked(dev) ((dev)->locked)
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+#else
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+#define dsp_lock_init(dev) do {} while (0)
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+#define dsp_lock(dev) do {} while (0)
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+#define dsp_unlock(dev) do {} while (0)
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+#define dsp_is_locked(dev) 0
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+#endif
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+
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/*
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* AZX stream operations.
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*/
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/* start a stream */
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-void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
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+static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
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{
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/*
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* Before stream start, initialize parameter
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@@ -53,7 +66,6 @@ void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
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azx_sd_readb(chip, azx_dev, SD_CTL) |
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SD_CTL_DMA_START | SD_INT_MASK);
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}
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-EXPORT_SYMBOL_GPL(azx_stream_start);
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/* stop DMA */
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static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
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@@ -75,7 +87,7 @@ void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
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EXPORT_SYMBOL_GPL(azx_stream_stop);
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/* reset stream */
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-void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
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+static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
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{
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unsigned char val;
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int timeout;
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@@ -103,12 +115,11 @@ void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
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/* reset first position - may not be synced with hw at this time */
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*azx_dev->posbuf = 0;
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}
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-EXPORT_SYMBOL_GPL(azx_stream_reset);
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/*
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* set up the SD for streaming
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*/
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-int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
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+static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
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{
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unsigned int val;
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/* make sure the run bit is zero for SD */
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@@ -152,7 +163,6 @@ int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
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return 0;
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}
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-EXPORT_SYMBOL_GPL(azx_setup_controller);
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/* assign a stream for the PCM */
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static inline struct azx_dev *
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@@ -267,10 +277,10 @@ static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
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/*
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* set up a BDL entry
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*/
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-int setup_bdle(struct azx *chip,
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- struct snd_dma_buffer *dmab,
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- struct azx_dev *azx_dev, u32 **bdlp,
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- int ofs, int size, int with_ioc)
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+static int setup_bdle(struct azx *chip,
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+ struct snd_dma_buffer *dmab,
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+ struct azx_dev *azx_dev, u32 **bdlp,
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+ int ofs, int size, int with_ioc)
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{
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u32 *bdl = *bdlp;
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@@ -306,7 +316,6 @@ int setup_bdle(struct azx *chip,
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*bdlp = bdl;
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return ofs;
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}
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-EXPORT_SYMBOL_GPL(setup_bdle);
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/*
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* set up BDL entries
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@@ -1014,6 +1023,124 @@ int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
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}
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EXPORT_SYMBOL_GPL(azx_attach_pcm_stream);
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+#ifdef CONFIG_SND_HDA_DSP_LOADER
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+/*
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+ * DSP loading code (e.g. for CA0132)
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+ */
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+
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+/* use the first stream for loading DSP */
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+static struct azx_dev *
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+azx_get_dsp_loader_dev(struct azx *chip)
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+{
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+ return &chip->azx_dev[chip->playback_index_offset];
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+}
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+
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+int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
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+ unsigned int byte_size,
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+ struct snd_dma_buffer *bufp)
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+{
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+ u32 *bdl;
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+ struct azx *chip = bus->private_data;
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+ struct azx_dev *azx_dev;
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+ int err;
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+
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+ azx_dev = azx_get_dsp_loader_dev(chip);
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+
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+ dsp_lock(azx_dev);
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+ spin_lock_irq(&chip->reg_lock);
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+ if (azx_dev->running || azx_dev->locked) {
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+ spin_unlock_irq(&chip->reg_lock);
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+ err = -EBUSY;
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+ goto unlock;
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+ }
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+ azx_dev->prepared = 0;
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+ chip->saved_azx_dev = *azx_dev;
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+ azx_dev->locked = 1;
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+ spin_unlock_irq(&chip->reg_lock);
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+
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+ err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV_SG,
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+ byte_size, bufp);
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+ if (err < 0)
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+ goto err_alloc;
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+
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+ azx_dev->bufsize = byte_size;
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+ azx_dev->period_bytes = byte_size;
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+ azx_dev->format_val = format;
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+
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+ azx_stream_reset(chip, azx_dev);
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+
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+ /* reset BDL address */
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+ azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
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+ azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
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+
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+ azx_dev->frags = 0;
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+ bdl = (u32 *)azx_dev->bdl.area;
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+ err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0);
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+ if (err < 0)
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+ goto error;
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+
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+ azx_setup_controller(chip, azx_dev);
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+ dsp_unlock(azx_dev);
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+ return azx_dev->stream_tag;
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+
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+ error:
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+ chip->ops->dma_free_pages(chip, bufp);
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+ err_alloc:
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+ spin_lock_irq(&chip->reg_lock);
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+ if (azx_dev->opened)
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+ *azx_dev = chip->saved_azx_dev;
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+ azx_dev->locked = 0;
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+ spin_unlock_irq(&chip->reg_lock);
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+ unlock:
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+ dsp_unlock(azx_dev);
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+ return err;
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+}
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+EXPORT_SYMBOL_GPL(azx_load_dsp_prepare);
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+
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+void azx_load_dsp_trigger(struct hda_bus *bus, bool start)
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+{
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+ struct azx *chip = bus->private_data;
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+ struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
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+
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+ if (start)
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+ azx_stream_start(chip, azx_dev);
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+ else
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+ azx_stream_stop(chip, azx_dev);
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+ azx_dev->running = start;
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+}
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+EXPORT_SYMBOL_GPL(azx_load_dsp_trigger);
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+
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+void azx_load_dsp_cleanup(struct hda_bus *bus,
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+ struct snd_dma_buffer *dmab)
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+{
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+ struct azx *chip = bus->private_data;
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+ struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
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+
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+ if (!dmab->area || !azx_dev->locked)
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+ return;
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+
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+ dsp_lock(azx_dev);
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+ /* reset BDL address */
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+ azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
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+ azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
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+ azx_sd_writel(chip, azx_dev, SD_CTL, 0);
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+ azx_dev->bufsize = 0;
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+ azx_dev->period_bytes = 0;
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+ azx_dev->format_val = 0;
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+
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+ chip->ops->dma_free_pages(chip, dmab);
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+ dmab->area = NULL;
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+
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+ spin_lock_irq(&chip->reg_lock);
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+ if (azx_dev->opened)
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+ *azx_dev = chip->saved_azx_dev;
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+ azx_dev->locked = 0;
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+ spin_unlock_irq(&chip->reg_lock);
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+ dsp_unlock(azx_dev);
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+}
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+EXPORT_SYMBOL_GPL(azx_load_dsp_cleanup);
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+#endif /* CONFIG_SND_HDA_DSP_LOADER */
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+
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int azx_alloc_stream_pages(struct azx *chip)
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{
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int i, err;
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