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@@ -96,11 +96,6 @@
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#define EXYNOS4412_MUX_ADDR_SHIFT 20
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/* Exynos5433 specific registers */
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-#define EXYNOS5433_TMU_REG_CONTROL1 0x024
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-#define EXYNOS5433_TMU_SAMPLING_INTERVAL 0x02c
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-#define EXYNOS5433_TMU_COUNTER_VALUE0 0x030
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-#define EXYNOS5433_TMU_COUNTER_VALUE1 0x034
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-#define EXYNOS5433_TMU_REG_CURRENT_TEMP1 0x044
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#define EXYNOS5433_THD_TEMP_RISE3_0 0x050
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#define EXYNOS5433_THD_TEMP_RISE7_4 0x054
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#define EXYNOS5433_THD_TEMP_FALL3_0 0x060
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