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@@ -52,6 +52,12 @@ mmio_list_base:
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#endif
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#endif
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#ifdef INCLUDE_CODE
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#ifdef INCLUDE_CODE
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+#define gpc_wr32(addr,reg) /*
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+*/ mov b32 $r15 reg /*
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+*/ imm32($r14, addr) /*
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+*/ or $r14 NV_PGRAPH_GPCX_GPCCS_MMIO_CTRL_BASE_ENABLE /*
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+*/ call(nv_wr32)
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+
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// reports an exception to the host
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// reports an exception to the host
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//
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//
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// In: $r15 error code (see os.h)
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// In: $r15 error code (see os.h)
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@@ -101,7 +107,7 @@ init:
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// enable interrupts
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// enable interrupts
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bset $flags ie0
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bset $flags ie0
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- // figure out which GPC we are, and how many TPCs we have
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+ // how many TPCs do we have?
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nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_UNITS, 0)
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nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_UNITS, 0)
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mov $r3 1
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mov $r3 1
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and $r2 0x1f
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and $r2 0x1f
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@@ -109,8 +115,12 @@ init:
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sub b32 $r3 1
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sub b32 $r3 1
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st b32 D[$r0 + #tpc_count] $r2
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st b32 D[$r0 + #tpc_count] $r2
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st b32 D[$r0 + #tpc_mask] $r3
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st b32 D[$r0 + #tpc_mask] $r3
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+
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+ // determine which GPC we are, setup (optional) mmio access offset
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nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_MYINDEX, 0)
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nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_MYINDEX, 0)
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st b32 D[$r0 + #gpc_id] $r2
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st b32 D[$r0 + #gpc_id] $r2
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+ shl b32 $r2 15
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+ nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMIO_BASE, 0, $r2)
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#if NV_PGRAPH_GPCX_UNK__SIZE > 0
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#if NV_PGRAPH_GPCX_UNK__SIZE > 0
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// figure out which, and how many, UNKs are actually present
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// figure out which, and how many, UNKs are actually present
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