|
@@ -451,7 +451,7 @@ int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
|
|
|
regs->cp0_epc + dec_insn.pc_inc +
|
|
|
dec_insn.next_pc_inc;
|
|
|
}
|
|
|
- /* Fall through */
|
|
|
+ /* fall through */
|
|
|
case jr_op:
|
|
|
/* For R6, JR already emulated in jalr_op */
|
|
|
if (NO_R6EMU && insn.r_format.func == jr_op)
|
|
@@ -471,10 +471,11 @@ int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
|
|
|
regs->regs[31] = regs->cp0_epc +
|
|
|
dec_insn.pc_inc +
|
|
|
dec_insn.next_pc_inc;
|
|
|
- /* Fall through */
|
|
|
+ /* fall through */
|
|
|
case bltzl_op:
|
|
|
if (NO_R6EMU)
|
|
|
break;
|
|
|
+ /* fall through */
|
|
|
case bltz_op:
|
|
|
if ((long)regs->regs[insn.i_format.rs] < 0)
|
|
|
*contpc = regs->cp0_epc +
|
|
@@ -494,10 +495,11 @@ int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
|
|
|
regs->regs[31] = regs->cp0_epc +
|
|
|
dec_insn.pc_inc +
|
|
|
dec_insn.next_pc_inc;
|
|
|
- /* Fall through */
|
|
|
+ /* fall through */
|
|
|
case bgezl_op:
|
|
|
if (NO_R6EMU)
|
|
|
break;
|
|
|
+ /* fall through */
|
|
|
case bgez_op:
|
|
|
if ((long)regs->regs[insn.i_format.rs] >= 0)
|
|
|
*contpc = regs->cp0_epc +
|
|
@@ -512,11 +514,12 @@ int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
|
|
|
break;
|
|
|
case jalx_op:
|
|
|
set_isa16_mode(bit);
|
|
|
+ /* fall through */
|
|
|
case jal_op:
|
|
|
regs->regs[31] = regs->cp0_epc +
|
|
|
dec_insn.pc_inc +
|
|
|
dec_insn.next_pc_inc;
|
|
|
- /* Fall through */
|
|
|
+ /* fall through */
|
|
|
case j_op:
|
|
|
*contpc = regs->cp0_epc + dec_insn.pc_inc;
|
|
|
*contpc >>= 28;
|
|
@@ -528,6 +531,7 @@ int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
|
|
|
case beql_op:
|
|
|
if (NO_R6EMU)
|
|
|
break;
|
|
|
+ /* fall through */
|
|
|
case beq_op:
|
|
|
if (regs->regs[insn.i_format.rs] ==
|
|
|
regs->regs[insn.i_format.rt])
|
|
@@ -542,6 +546,7 @@ int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
|
|
|
case bnel_op:
|
|
|
if (NO_R6EMU)
|
|
|
break;
|
|
|
+ /* fall through */
|
|
|
case bne_op:
|
|
|
if (regs->regs[insn.i_format.rs] !=
|
|
|
regs->regs[insn.i_format.rt])
|
|
@@ -556,6 +561,7 @@ int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
|
|
|
case blezl_op:
|
|
|
if (!insn.i_format.rt && NO_R6EMU)
|
|
|
break;
|
|
|
+ /* fall through */
|
|
|
case blez_op:
|
|
|
|
|
|
/*
|
|
@@ -593,6 +599,7 @@ int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
|
|
|
case bgtzl_op:
|
|
|
if (!insn.i_format.rt && NO_R6EMU)
|
|
|
break;
|
|
|
+ /* fall through */
|
|
|
case bgtz_op:
|
|
|
/*
|
|
|
* Compact branches for R6 for the
|
|
@@ -729,7 +736,8 @@ int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
|
|
|
|
|
|
return 1;
|
|
|
}
|
|
|
- /* R2/R6 compatible cop1 instruction. Fall through */
|
|
|
+ /* R2/R6 compatible cop1 instruction */
|
|
|
+ /* fall through */
|
|
|
case cop2_op:
|
|
|
case cop1x_op:
|
|
|
if (insn.i_format.rs == bc_op) {
|
|
@@ -1221,14 +1229,14 @@ emul:
|
|
|
case bcfl_op:
|
|
|
if (cpu_has_mips_2_3_4_5_r)
|
|
|
likely = 1;
|
|
|
- /* Fall through */
|
|
|
+ /* fall through */
|
|
|
case bcf_op:
|
|
|
cond = !cond;
|
|
|
break;
|
|
|
case bctl_op:
|
|
|
if (cpu_has_mips_2_3_4_5_r)
|
|
|
likely = 1;
|
|
|
- /* Fall through */
|
|
|
+ /* fall through */
|
|
|
case bct_op:
|
|
|
break;
|
|
|
}
|