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@@ -292,8 +292,6 @@
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#define SPRN_HRMOR 0x139 /* Real mode offset register */
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#define SPRN_HSRR0 0x13A /* Hypervisor Save/Restore 0 */
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#define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */
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-#define SPRN_LMRR 0x32D /* Load Monitor Region Register */
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-#define SPRN_LMSER 0x32E /* Load Monitor Section Enable Register */
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#define SPRN_IC 0x350 /* Virtual Instruction Count */
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#define SPRN_VTB 0x351 /* Virtual Time Base */
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#define SPRN_LDBAR 0x352 /* LD Base Address Register */
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@@ -304,7 +302,6 @@
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#define SPRN_PMCR 0x374 /* Power Management Control Register */
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/* HFSCR and FSCR bit numbers are the same */
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-#define FSCR_LM_LG 11 /* Enable Load Monitor Registers */
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#define FSCR_TAR_LG 8 /* Enable Target Address Register */
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#define FSCR_EBB_LG 7 /* Enable Event Based Branching */
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#define FSCR_TM_LG 5 /* Enable Transactional Memory */
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@@ -314,12 +311,10 @@
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#define FSCR_VECVSX_LG 1 /* Enable VMX/VSX */
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#define FSCR_FP_LG 0 /* Enable Floating Point */
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#define SPRN_FSCR 0x099 /* Facility Status & Control Register */
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-#define FSCR_LM __MASK(FSCR_LM_LG)
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#define FSCR_TAR __MASK(FSCR_TAR_LG)
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#define FSCR_EBB __MASK(FSCR_EBB_LG)
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#define FSCR_DSCR __MASK(FSCR_DSCR_LG)
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#define SPRN_HFSCR 0xbe /* HV=1 Facility Status & Control Register */
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-#define HFSCR_LM __MASK(FSCR_LM_LG)
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#define HFSCR_TAR __MASK(FSCR_TAR_LG)
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#define HFSCR_EBB __MASK(FSCR_EBB_LG)
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#define HFSCR_TM __MASK(FSCR_TM_LG)
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