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@@ -1896,7 +1896,7 @@ static int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
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enum rtl8xxxu_rfpath path, u8 reg, u32 data)
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{
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int ret, retval;
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- u32 dataaddr;
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+ u32 dataaddr, val32;
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if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
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dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
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@@ -1905,6 +1905,12 @@ static int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
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data &= FPGA0_LSSI_PARM_DATA_MASK;
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dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
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+ if (priv->rtl_chip == RTL8192E) {
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+ val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
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+ val32 &= ~0x20000;
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+ rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
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+ }
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+
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/* Use XB for path B */
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ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
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if (ret != sizeof(dataaddr))
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@@ -1914,6 +1920,12 @@ static int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
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udelay(1);
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+ if (priv->rtl_chip == RTL8192E) {
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+ val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
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+ val32 |= 0x20000;
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+ rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
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+ }
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+
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return retval;
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}
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