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@@ -321,6 +321,10 @@ static void amdgpu_vce_idle_work_handler(struct work_struct *work)
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amdgpu_dpm_enable_vce(adev, false);
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} else {
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amdgpu_asic_set_vce_clocks(adev, 0, 0);
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+ amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
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+ AMD_PG_STATE_GATE);
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+ amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
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+ AMD_CG_STATE_GATE);
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}
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} else {
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schedule_delayed_work(&adev->vce.idle_work, VCE_IDLE_TIMEOUT);
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@@ -346,6 +350,11 @@ void amdgpu_vce_ring_begin_use(struct amdgpu_ring *ring)
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amdgpu_dpm_enable_vce(adev, true);
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} else {
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amdgpu_asic_set_vce_clocks(adev, 53300, 40000);
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+ amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
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+ AMD_CG_STATE_UNGATE);
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+ amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
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+ AMD_PG_STATE_UNGATE);
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+
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}
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}
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mutex_unlock(&adev->vce.idle_mutex);
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