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@@ -87,6 +87,19 @@ static int aq_fw2x_set_link_speed(struct aq_hw_s *self, u32 speed)
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return 0;
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}
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+static void aq_fw2x_set_mpi_flow_control(struct aq_hw_s *self, u32 *mpi_state)
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+{
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+ if (self->aq_nic_cfg->flow_control & AQ_NIC_FC_RX)
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+ *mpi_state |= BIT(CAPS_HI_PAUSE);
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+ else
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+ *mpi_state &= ~BIT(CAPS_HI_PAUSE);
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+
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+ if (self->aq_nic_cfg->flow_control & AQ_NIC_FC_TX)
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+ *mpi_state |= BIT(CAPS_HI_ASYMMETRIC_PAUSE);
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+ else
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+ *mpi_state &= ~BIT(CAPS_HI_ASYMMETRIC_PAUSE);
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+}
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+
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static int aq_fw2x_set_state(struct aq_hw_s *self,
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enum hal_atl_utils_fw_state_e state)
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{
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@@ -95,6 +108,7 @@ static int aq_fw2x_set_state(struct aq_hw_s *self,
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switch (state) {
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case MPI_INIT:
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mpi_state &= ~BIT(CAPS_HI_LINK_DROP);
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+ aq_fw2x_set_mpi_flow_control(self, &mpi_state);
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break;
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case MPI_DEINIT:
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mpi_state |= BIT(CAPS_HI_LINK_DROP);
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@@ -201,6 +215,17 @@ static int aq_fw2x_update_stats(struct aq_hw_s *self)
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return hw_atl_utils_update_stats(self);
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}
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+static int aq_fw2x_set_flow_control(struct aq_hw_s *self)
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+{
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+ u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
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+
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+ aq_fw2x_set_mpi_flow_control(self, &mpi_state);
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+
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+ aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_state);
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+
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+ return 0;
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+}
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+
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const struct aq_fw_ops aq_fw_2x_ops = {
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.init = aq_fw2x_init,
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.deinit = aq_fw2x_deinit,
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@@ -210,4 +235,5 @@ const struct aq_fw_ops aq_fw_2x_ops = {
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.set_state = aq_fw2x_set_state,
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.update_link_status = aq_fw2x_update_link_status,
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.update_stats = aq_fw2x_update_stats,
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+ .set_flow_control = aq_fw2x_set_flow_control,
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};
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