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@@ -2169,16 +2169,8 @@ static struct omap_hwmod omap3xxx_gpmc_hwmod = {
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.clkdm_name = "core_l3_clkdm",
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.mpu_irqs = omap3xxx_gpmc_irqs,
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.main_clk = "gpmc_fck",
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- /*
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- * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
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- * block. It is not being added due to any known bugs with
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- * resetting the GPMC IP block, but rather because any timings
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- * set by the bootloader are not being correctly programmed by
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- * the kernel from the board file or DT data.
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- * HWMOD_INIT_NO_RESET should be removed ASAP.
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- */
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- .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
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- HWMOD_NO_IDLEST),
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+ /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
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+ .flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
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};
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/*
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@@ -3744,29 +3736,54 @@ static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
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/* GP-only hwmod links */
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static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = {
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&omap3xxx_l4_sec__timer12,
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- &omap3xxx_l4_core__sham,
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- &omap3xxx_l4_core__aes,
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NULL
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};
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static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = {
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&omap3xxx_l4_sec__timer12,
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- &omap3xxx_l4_core__sham,
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- &omap3xxx_l4_core__aes,
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NULL
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};
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static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = {
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&omap3xxx_l4_sec__timer12,
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- /*
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- * Apparently the SHA/MD5 and AES accelerator IP blocks are
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- * only present on some AM35xx chips, and no one knows which
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- * ones. See
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- * http://www.spinics.net/lists/arm-kernel/msg215466.html So
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- * if you need these IP blocks on an AM35xx, try uncommenting
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- * the following lines.
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- */
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+ NULL
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+};
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+
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+/* crypto hwmod links */
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+static struct omap_hwmod_ocp_if *omap34xx_sham_hwmod_ocp_ifs[] __initdata = {
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+ &omap3xxx_l4_core__sham,
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+ NULL
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+};
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+
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+static struct omap_hwmod_ocp_if *omap34xx_aes_hwmod_ocp_ifs[] __initdata = {
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+ &omap3xxx_l4_core__aes,
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+ NULL
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+};
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+
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+static struct omap_hwmod_ocp_if *omap36xx_sham_hwmod_ocp_ifs[] __initdata = {
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+ &omap3xxx_l4_core__sham,
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+ NULL
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+};
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+
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+static struct omap_hwmod_ocp_if *omap36xx_aes_hwmod_ocp_ifs[] __initdata = {
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+ &omap3xxx_l4_core__aes,
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+ NULL
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+};
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+
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+/*
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+ * Apparently the SHA/MD5 and AES accelerator IP blocks are
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+ * only present on some AM35xx chips, and no one knows which
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+ * ones. See
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+ * http://www.spinics.net/lists/arm-kernel/msg215466.html So
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+ * if you need these IP blocks on an AM35xx, try uncommenting
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+ * the following lines.
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+ */
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+static struct omap_hwmod_ocp_if *am35xx_sham_hwmod_ocp_ifs[] __initdata = {
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/* &omap3xxx_l4_core__sham, */
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+ NULL
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+};
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+
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+static struct omap_hwmod_ocp_if *am35xx_aes_hwmod_ocp_ifs[] __initdata = {
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/* &omap3xxx_l4_core__aes, */
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NULL
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};
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@@ -3868,10 +3885,41 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
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NULL
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};
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+/**
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+ * omap3xxx_hwmod_is_hs_ip_block_usable - is a security IP block accessible?
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+ * @bus: struct device_node * for the top-level OMAP DT data
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+ * @dev_name: device name used in the DT file
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+ *
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+ * Determine whether a "secure" IP block @dev_name is usable by Linux.
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+ * There doesn't appear to be a 100% reliable way to determine this,
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+ * so we rely on heuristics. If @bus is null, meaning there's no DT
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+ * data, then we only assume the IP block is accessible if the OMAP is
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+ * fused as a 'general-purpose' SoC. If however DT data is present,
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+ * test to see if the IP block is described in the DT data and set to
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+ * 'status = "okay"'. If so then we assume the ODM has configured the
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+ * OMAP firewalls to allow access to the IP block.
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+ *
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+ * Return: 0 if device named @dev_name is not likely to be accessible,
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+ * or 1 if it is likely to be accessible.
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+ */
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+static int __init omap3xxx_hwmod_is_hs_ip_block_usable(struct device_node *bus,
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+ const char *dev_name)
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+{
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+ if (!bus)
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+ return (omap_type() == OMAP2_DEVICE_TYPE_GP) ? 1 : 0;
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+
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+ if (of_device_is_available(of_find_node_by_name(bus, dev_name)))
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+ return 1;
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+
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+ return 0;
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+}
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+
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int __init omap3xxx_hwmod_init(void)
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{
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int r;
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- struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL;
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+ struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL, **h_sham = NULL;
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+ struct omap_hwmod_ocp_if **h_aes = NULL;
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+ struct device_node *bus = NULL;
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unsigned int rev;
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omap_hwmod_init();
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@@ -3893,13 +3941,19 @@ int __init omap3xxx_hwmod_init(void)
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rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
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h = omap34xx_hwmod_ocp_ifs;
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h_gp = omap34xx_gp_hwmod_ocp_ifs;
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+ h_sham = omap34xx_sham_hwmod_ocp_ifs;
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+ h_aes = omap34xx_aes_hwmod_ocp_ifs;
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} else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
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h = am35xx_hwmod_ocp_ifs;
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h_gp = am35xx_gp_hwmod_ocp_ifs;
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+ h_sham = am35xx_sham_hwmod_ocp_ifs;
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+ h_aes = am35xx_aes_hwmod_ocp_ifs;
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} else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
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rev == OMAP3630_REV_ES1_2) {
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h = omap36xx_hwmod_ocp_ifs;
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h_gp = omap36xx_gp_hwmod_ocp_ifs;
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+ h_sham = omap36xx_sham_hwmod_ocp_ifs;
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+ h_aes = omap36xx_aes_hwmod_ocp_ifs;
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} else {
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WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
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return -EINVAL;
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@@ -3916,6 +3970,25 @@ int __init omap3xxx_hwmod_init(void)
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return r;
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}
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+ /*
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+ * Register crypto hwmod links only if they are not disabled in DT.
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+ * If DT information is missing, enable them only for GP devices.
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+ */
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+
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+ if (of_have_populated_dt())
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+ bus = of_find_node_by_name(NULL, "ocp");
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+
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+ if (h_sham && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "sham")) {
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+ r = omap_hwmod_register_links(h_sham);
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+ if (r < 0)
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+ return r;
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+ }
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+
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+ if (h_aes && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "aes")) {
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+ r = omap_hwmod_register_links(h_aes);
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+ if (r < 0)
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+ return r;
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+ }
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/*
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* Register hwmod links specific to certain ES levels of a
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Kevin Hilman