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@@ -959,21 +959,15 @@ static int uvd_v6_0_set_clockgating_state(void *handle,
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enum amd_clockgating_state state)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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- bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
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- static int curstate = -1;
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-
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- if (adev->asic_type == CHIP_FIJI ||
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- adev->asic_type == CHIP_POLARIS10)
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- uvd_v6_set_bypass_mode(adev, enable);
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if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
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return 0;
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- if (curstate == state)
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- return 0;
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+ if (adev->asic_type == CHIP_FIJI ||
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+ adev->asic_type == CHIP_POLARIS10)
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+ uvd_v6_set_bypass_mode(adev, state == AMD_CG_STATE_GATE ? true : false);
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- curstate = state;
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- if (enable) {
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+ if (state == AMD_CG_STATE_GATE) {
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/* disable HW gating and enable Sw gating */
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uvd_v6_0_set_sw_clock_gating(adev);
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} else {
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