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@@ -8348,6 +8348,49 @@ static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index,
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mlxsw_reg_mgpc_opcode_set(payload, opcode);
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mlxsw_reg_mgpc_opcode_set(payload, opcode);
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}
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}
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+/* MPRS - Monitoring Parsing State Register
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+ * ----------------------------------------
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+ * The MPRS register is used for setting up the parsing for hash,
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+ * policy-engine and routing.
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+ */
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+#define MLXSW_REG_MPRS_ID 0x9083
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+#define MLXSW_REG_MPRS_LEN 0x14
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+
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+MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN);
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+
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+/* reg_mprs_parsing_depth
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+ * Minimum parsing depth.
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+ * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL
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+ * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2.
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+ * Access: RW
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+ */
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+MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16);
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+
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+/* reg_mprs_parsing_en
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+ * Parsing enable.
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+ * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and
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+ * NVGRE. Default is enabled. Reserved when SwitchX-2.
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+ * Access: RW
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+ */
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+MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16);
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+
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+/* reg_mprs_vxlan_udp_dport
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+ * VxLAN UDP destination port.
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+ * Used for identifying VxLAN packets and for dport field in
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+ * encapsulation. Default is 4789.
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+ * Access: RW
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+ */
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+MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16);
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+
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+static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth,
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+ u16 vxlan_udp_dport)
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+{
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+ MLXSW_REG_ZERO(mprs, payload);
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+ mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth);
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+ mlxsw_reg_mprs_parsing_en_set(payload, true);
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+ mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport);
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+}
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+
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/* TNGCR - Tunneling NVE General Configuration Register
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/* TNGCR - Tunneling NVE General Configuration Register
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* ----------------------------------------------------
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* ----------------------------------------------------
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* The TNGCR register is used for setting up the NVE Tunneling configuration.
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* The TNGCR register is used for setting up the NVE Tunneling configuration.
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@@ -9356,6 +9399,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
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MLXSW_REG(mcc),
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MLXSW_REG(mcc),
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MLXSW_REG(mcda),
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MLXSW_REG(mcda),
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MLXSW_REG(mgpc),
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MLXSW_REG(mgpc),
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+ MLXSW_REG(mprs),
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MLXSW_REG(tngcr),
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MLXSW_REG(tngcr),
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MLXSW_REG(tnumt),
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MLXSW_REG(tnumt),
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MLXSW_REG(tnqcr),
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MLXSW_REG(tnqcr),
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