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i2c: mlxcpld: Add capability register description to documentation

It adds capability register description to documentation.

Signed-off-by: Michael Shych <michaelsh@mellanox.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Michael Shych 7 years ago
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      Documentation/i2c/busses/i2c-mlxcpld

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Documentation/i2c/busses/i2c-mlxcpld
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@@ -20,6 +20,10 @@ The next transaction types are supported:
 
  - Write Byte/Block.
 
  - Write Byte/Block.
 
 
 
 Registers:
 
 Registers:
 
+CPBLTY		0x0 - capability reg.
 
+			Bits [6:5] - transaction length. b01 - 72B is supported,
 
+			36B in other case.
 
+			Bit 7 - SMBus block read support.
 
 CTRL		0x1 - control reg.
 
 CTRL		0x1 - control reg.
 
 			Resets all the registers.
 
 			Resets all the registers.
 
 HALF_CYC	0x4 - cycle reg.
 
 HALF_CYC	0x4 - cycle reg.