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+/*
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+ * This file is part of the Chelsio T4 Ethernet driver for Linux.
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+ *
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+ * Copyright (c) 2003-2015 Chelsio Communications, Inc. All rights reserved.
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+ *
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+ * This software is available to you under a choice of one of two
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+ * licenses. You may choose to be licensed under the terms of the GNU
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+ * General Public License (GPL) Version 2, available from the file
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+ * COPYING in the main directory of this source tree, or the
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+ * OpenIB.org BSD license below:
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+ *
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+ * Redistribution and use in source and binary forms, with or
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+ * without modification, are permitted provided that the following
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+ * conditions are met:
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+ *
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+ * - Redistributions of source code must retain the above
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+ * copyright notice, this list of conditions and the following
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+ * disclaimer.
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+ *
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+ * - Redistributions in binary form must reproduce the above
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+ * copyright notice, this list of conditions and the following
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+ * disclaimer in the documentation and/or other materials
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+ * provided with the distribution.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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+ * SOFTWARE.
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+ */
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+#ifndef __T4_CHIP_TYPE_H__
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+#define __T4_CHIP_TYPE_H__
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+
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+#define CHELSIO_T4 0x4
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+#define CHELSIO_T5 0x5
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+#define CHELSIO_T6 0x6
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+
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+/* We code the Chelsio T4 Family "Chip Code" as a tuple:
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+ *
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+ * (Chip Version, Chip Revision)
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+ *
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+ * where:
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+ *
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+ * Chip Version: is T4, T5, etc.
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+ * Chip Revision: is the FAB "spin" of the Chip Version.
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+ */
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+#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
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+#define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf)
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+#define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
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+
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+enum chip_type {
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+ T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
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+ T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2),
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+ T4_FIRST_REV = T4_A1,
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+ T4_LAST_REV = T4_A2,
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+
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+ T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
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+ T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
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+ T5_FIRST_REV = T5_A0,
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+ T5_LAST_REV = T5_A1,
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+
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+ T6_A0 = CHELSIO_CHIP_CODE(CHELSIO_T6, 0),
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+ T6_FIRST_REV = T6_A0,
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+ T6_LAST_REV = T6_A0,
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+};
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+
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+static inline int is_t4(enum chip_type chip)
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+{
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+ return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4);
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+}
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+
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+static inline int is_t5(enum chip_type chip)
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+{
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+ return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5);
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+}
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+
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+static inline int is_t6(enum chip_type chip)
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+{
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+ return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6);
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+}
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+
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+#endif /* __T4_CHIP_TYPE_H__ */
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Hariprasad S