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@@ -40,8 +40,8 @@
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#define MWIFIEX_TXBD_MASK 0x3F
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#define MWIFIEX_RXBD_MASK 0x3F
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-#define MWIFIEX_MAX_EVT_BD 0x04
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-#define MWIFIEX_EVTBD_MASK 0x07
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+#define MWIFIEX_MAX_EVT_BD 0x08
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+#define MWIFIEX_EVTBD_MASK 0x0f
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/* PCIE INTERNAL REGISTERS */
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#define PCIE_SCRATCH_0_REG 0xC10
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@@ -69,6 +69,7 @@
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#define CPU_INTR_DOOR_BELL BIT(1)
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#define CPU_INTR_SLEEP_CFM_DONE BIT(2)
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#define CPU_INTR_RESET BIT(3)
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+#define CPU_INTR_EVENT_DONE BIT(5)
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#define HOST_INTR_DNLD_DONE BIT(0)
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#define HOST_INTR_UPLD_RDY BIT(1)
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