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@@ -21,6 +21,7 @@
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/* A64 instructions are always 32 bits. */
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#define AARCH64_INSN_SIZE 4
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+#ifndef __ASSEMBLY__
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/*
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* ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
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* Section C3.1 "A64 instruction index by encoding":
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@@ -104,5 +105,6 @@ bool aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn);
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int aarch64_insn_patch_text_nosync(void *addr, u32 insn);
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int aarch64_insn_patch_text_sync(void *addrs[], u32 insns[], int cnt);
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int aarch64_insn_patch_text(void *addrs[], u32 insns[], int cnt);
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+#endif /* __ASSEMBLY__ */
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#endif /* __ASM_INSN_H */
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