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@@ -259,6 +259,8 @@ static const struct pinctrl_pin_desc imx7ulp_pinctrl_pads[] = {
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IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF19),
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};
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+#define BM_OBE_ENABLED BIT(17)
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+#define BM_IBE_ENABLED BIT(16)
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#define BM_LK_ENABLED BIT(15)
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#define BM_MUX_MODE 0xf00
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#define BP_MUX_MODE 8
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@@ -300,10 +302,34 @@ static void imx7ulp_cfg_params_fixup(unsigned long *configs,
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}
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}
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+static int imx7ulp_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
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+ struct pinctrl_gpio_range *range,
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+ unsigned offset, bool input)
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+{
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+ struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
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+ struct imx_pinctrl_soc_info *info = ipctl->info;
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+ const struct imx_pin_reg *pin_reg;
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+ u32 reg;
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+
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+ pin_reg = &info->pin_regs[offset];
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+ if (pin_reg->mux_reg == -1)
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+ return -EINVAL;
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+
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+ reg = readl(ipctl->base + pin_reg->mux_reg);
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+ if (input)
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+ reg = (reg & ~BM_OBE_ENABLED) | BM_IBE_ENABLED;
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+ else
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+ reg = (reg & ~BM_IBE_ENABLED) | BM_OBE_ENABLED;
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+ writel(reg, ipctl->base + pin_reg->mux_reg);
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+
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+ return 0;
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+}
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+
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static struct imx_pinctrl_soc_info imx7ulp_pinctrl_info = {
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.pins = imx7ulp_pinctrl_pads,
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.npins = ARRAY_SIZE(imx7ulp_pinctrl_pads),
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.flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG,
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+ .gpio_set_direction = imx7ulp_pmx_gpio_set_direction,
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.mux_mask = BM_MUX_MODE,
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.mux_shift = BP_MUX_MODE,
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.generic_pinconf = true,
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