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@@ -125,7 +125,9 @@
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FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
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/* FLEXCAN interrupt flag register (IFLAG) bits */
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-#define FLEXCAN_TX_BUF_ID 8
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+/* Errata ERR005829 step7: Reserve first valid MB */
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+#define FLEXCAN_TX_BUF_RESERVED 8
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+#define FLEXCAN_TX_BUF_ID 9
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#define FLEXCAN_IFLAG_BUF(x) BIT(x)
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#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
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#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
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@@ -439,6 +441,14 @@ static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
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flexcan_write(can_id, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_id);
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flexcan_write(ctrl, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
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+ /* Errata ERR005829 step8:
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+ * Write twice INACTIVE(0x8) code to first MB.
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+ */
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+ flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
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+ ®s->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
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+ flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
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+ ®s->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
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+
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return NETDEV_TX_OK;
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}
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@@ -885,6 +895,10 @@ static int flexcan_chip_start(struct net_device *dev)
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®s->cantxfg[i].can_ctrl);
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}
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+ /* Errata ERR005829: mark first TX mailbox as INACTIVE */
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+ flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
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+ ®s->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
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+
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/* mark TX mailbox as INACTIVE */
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flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
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®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
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