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@@ -28,6 +28,7 @@
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#include "vid.h"
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#include "vid.h"
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#include "amdgpu_ucode.h"
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#include "amdgpu_ucode.h"
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#include "amdgpu_atombios.h"
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#include "amdgpu_atombios.h"
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+#include "atombios_i2c.h"
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#include "clearstate_vi.h"
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#include "clearstate_vi.h"
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#include "gmc/gmc_8_2_d.h"
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#include "gmc/gmc_8_2_d.h"
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@@ -284,6 +285,7 @@ static const u32 golden_settings_polaris11_a11[] =
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mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3,
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mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3,
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mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
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mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
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mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210,
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mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210,
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+ mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
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};
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};
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static const u32 polaris11_golden_common_all[] =
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static const u32 polaris11_golden_common_all[] =
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@@ -314,6 +316,7 @@ static const u32 golden_settings_polaris10_a11[] =
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mmTCC_CTRL, 0x00100000, 0xf31fff7f,
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mmTCC_CTRL, 0x00100000, 0xf31fff7f,
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mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
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mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
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mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
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mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
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+ mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
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};
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};
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static const u32 polaris10_golden_common_all[] =
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static const u32 polaris10_golden_common_all[] =
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@@ -696,6 +699,10 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
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polaris10_golden_common_all,
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polaris10_golden_common_all,
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(const u32)ARRAY_SIZE(polaris10_golden_common_all));
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(const u32)ARRAY_SIZE(polaris10_golden_common_all));
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WREG32_SMC(ixCG_ACLK_CNTL, 0x0000001C);
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WREG32_SMC(ixCG_ACLK_CNTL, 0x0000001C);
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+ if (adev->pdev->revision == 0xc7) {
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+ amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1E, 0xDD);
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+ amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1F, 0xD0);
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+ }
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break;
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break;
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case CHIP_CARRIZO:
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case CHIP_CARRIZO:
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amdgpu_program_register_sequence(adev,
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amdgpu_program_register_sequence(adev,
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