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@@ -26,6 +26,38 @@
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#include "amdgpu.h"
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+/**
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+ * amdgpu_gmc_get_pde_for_bo - get the PDE for a BO
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+ *
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+ * @bo: the BO to get the PDE for
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+ * @level: the level in the PD hirarchy
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+ * @addr: resulting addr
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+ * @flags: resulting flags
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+ *
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+ * Get the address and flags to be used for a PDE (Page Directory Entry).
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+ */
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+void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
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+ uint64_t *addr, uint64_t *flags)
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+{
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+ struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
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+ struct ttm_dma_tt *ttm;
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+
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+ switch (bo->tbo.mem.mem_type) {
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+ case TTM_PL_TT:
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+ ttm = container_of(bo->tbo.ttm, struct ttm_dma_tt, ttm);
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+ *addr = ttm->dma_address[0];
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+ break;
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+ case TTM_PL_VRAM:
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+ *addr = amdgpu_bo_gpu_offset(bo);
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+ break;
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+ default:
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+ *addr = 0;
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+ break;
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+ }
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+ *flags = amdgpu_ttm_tt_pde_flags(bo->tbo.ttm, &bo->tbo.mem);
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+ amdgpu_gmc_get_vm_pde(adev, level, addr, flags);
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+}
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+
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/**
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* amdgpu_gmc_pd_addr - return the address of the root directory
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*
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@@ -35,13 +67,14 @@ uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo)
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struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
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uint64_t pd_addr;
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- pd_addr = amdgpu_bo_gpu_offset(bo);
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/* TODO: move that into ASIC specific code */
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if (adev->asic_type >= CHIP_VEGA10) {
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uint64_t flags = AMDGPU_PTE_VALID;
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- amdgpu_gmc_get_vm_pde(adev, -1, &pd_addr, &flags);
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+ amdgpu_gmc_get_pde_for_bo(bo, -1, &pd_addr, &flags);
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pd_addr |= flags;
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+ } else {
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+ pd_addr = amdgpu_bo_gpu_offset(bo);
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}
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return pd_addr;
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}
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