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@@ -60,7 +60,8 @@
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#define STM32_DMA_SCR_PINC BIT(9) /* Peripheral increment mode */
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#define STM32_DMA_SCR_CIRC BIT(8) /* Circular mode */
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#define STM32_DMA_SCR_PFCTRL BIT(5) /* Peripheral Flow Controller */
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-#define STM32_DMA_SCR_TCIE BIT(4) /* Transfer Cplete Int Enable*/
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+#define STM32_DMA_SCR_TCIE BIT(4) /* Transfer Complete Int Enable
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+ */
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#define STM32_DMA_SCR_TEIE BIT(2) /* Transfer Error Int Enable */
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#define STM32_DMA_SCR_DMEIE BIT(1) /* Direct Mode Err Int Enable */
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#define STM32_DMA_SCR_EN BIT(0) /* Stream Enable */
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@@ -918,7 +919,7 @@ static enum dma_status stm32_dma_tx_status(struct dma_chan *c,
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u32 residue = 0;
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status = dma_cookie_status(c, cookie, state);
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- if ((status == DMA_COMPLETE) || (!state))
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+ if (status == DMA_COMPLETE || !state)
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return status;
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spin_lock_irqsave(&chan->vchan.lock, flags);
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@@ -982,7 +983,7 @@ static void stm32_dma_desc_free(struct virt_dma_desc *vdesc)
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}
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static void stm32_dma_set_config(struct stm32_dma_chan *chan,
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- struct stm32_dma_cfg *cfg)
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+ struct stm32_dma_cfg *cfg)
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{
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stm32_dma_clear_reg(&chan->chan_reg);
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@@ -1015,8 +1016,8 @@ static struct dma_chan *stm32_dma_of_xlate(struct of_phandle_args *dma_spec,
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cfg.stream_config = dma_spec->args[2];
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cfg.features = dma_spec->args[3];
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- if ((cfg.channel_id >= STM32_DMA_MAX_CHANNELS) ||
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- (cfg.request_line >= STM32_DMA_MAX_REQUEST_ID)) {
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+ if (cfg.channel_id >= STM32_DMA_MAX_CHANNELS ||
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+ cfg.request_line >= STM32_DMA_MAX_REQUEST_ID) {
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dev_err(dev, "Bad channel and/or request id\n");
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return NULL;
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}
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