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@@ -1409,6 +1409,15 @@ static int ring_timestamp_mmio_read(struct intel_vgpu *vgpu,
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return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
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}
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+static int instdone_mmio_read(struct intel_vgpu *vgpu,
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+ unsigned int offset, void *p_data, unsigned int bytes)
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+{
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+ struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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+
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+ vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset));
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+ return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
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+}
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+
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static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
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void *p_data, unsigned int bytes)
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{
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@@ -1593,6 +1602,12 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
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MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
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#undef RING_REG
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+#define RING_REG(base) (base + 0x6c)
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+ MMIO_RING_DFH(RING_REG, D_ALL, 0, instdone_mmio_read, NULL);
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+ MMIO_DH(RING_REG(GEN8_BSD2_RING_BASE), D_ALL, instdone_mmio_read, NULL);
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+#undef RING_REG
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+ MMIO_DH(GEN7_SC_INSTDONE, D_HSW_PLUS, instdone_mmio_read, NULL);
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+
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MMIO_GM_RDR(0x2148, D_ALL, NULL, NULL);
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MMIO_GM_RDR(CCID, D_ALL, NULL, NULL);
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MMIO_GM_RDR(0x12198, D_ALL, NULL, NULL);
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