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@@ -207,6 +207,7 @@
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#define MV88E6185_G1_CTL2_CASCADE_PORT_MASK 0xf000
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#define MV88E6185_G1_CTL2_CASCADE_PORT_MASK 0xf000
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#define MV88E6185_G1_CTL2_CASCADE_PORT_NONE 0xe000
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#define MV88E6185_G1_CTL2_CASCADE_PORT_NONE 0xe000
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#define MV88E6185_G1_CTL2_CASCADE_PORT_MULTI 0xf000
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#define MV88E6185_G1_CTL2_CASCADE_PORT_MULTI 0xf000
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+#define MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK 0x001f
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/* Offset 0x1D: Stats Operation Register */
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/* Offset 0x1D: Stats Operation Register */
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#define MV88E6XXX_G1_STATS_OP 0x1d
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#define MV88E6XXX_G1_STATS_OP 0x1d
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@@ -256,6 +257,8 @@ int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);
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int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port);
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int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port);
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+int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index);
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+
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int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip *chip, bool learn2all);
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int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip *chip, bool learn2all);
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int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip *chip,
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int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip *chip,
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unsigned int msecs);
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unsigned int msecs);
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